[PATCH 1/4] mtd: spi: renesas: Extract strobe delay setting code into separate function

[Marek Vasut]

From: Hai Pham <hai.pham.ud at renesas.com>

Move strobe delay setting code into extra function and reflect the latest
setting in datasheet (R-Car Gen3 v2.20, R-Car V3U v0.50).
i.e. STRTIM[2:0] should be set to 110 (RCar M3-W) or 111 (Other products)

This is also a preparation for new R-Car Gen4 SoC which has 4-bits STRTIM

Reviewed-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud at renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org> # Fix for RZ/A1
---
Cc: Jagan Teki <jagan at amarulasolutions.com>
Cc: Vignesh R <vigneshr at ti.com>
---
 drivers/spi/renesas_rpc_spi.c | 29 +++++++++++++++++++++--------
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index cb2b8fb64de..07ff2d29fd4 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -202,18 +202,31 @@ static void rpc_spi_flush_read_cache(struct udevice *dev)
 
 }
 
+static u32 rpc_spi_get_strobe_delay(void)
+{
+#ifndef CONFIG_RZA1
+	u32 cpu_type = rmobile_get_cpu_type();
+
+	/*
+	 * NOTE: RPC_PHYCNT_STRTIM value:
+	 *       0: On H3 ES1.x (not supported in mainline U-Boot)
+	 *       6: On M3 ES1.x
+	 *       7: On other R-Car Gen3
+	 */
+	if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1)
+		return RPC_PHYCNT_STRTIM(6);
+	else
+#endif
+		return RPC_PHYCNT_STRTIM(7);
+}
+
 static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
 {
 	struct udevice *bus = dev->parent;
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
-	/*
-	 * NOTE: The 0x260 are undocumented bits, but they must be set.
-	 * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
-	 *       RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
-	 *       RPC_PHYCNT_STRTIM shall be 6.
-	 */
-	writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
+	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
+	writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
 	       priv->regs + RPC_PHYCNT);
 	writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
 		 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
@@ -233,7 +246,7 @@ static int rpc_spi_release_bus(struct udevice *dev)
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
 	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
-	writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
+	writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT);
 
 	rpc_spi_flush_read_cache(dev);
 
-- 
2.39.2