[PATCH v2 00/17] rockchip: eMMC fixes for RK3568 and support for RK3588
Eugen Hristev
eugen.hristev at collabora.com
Thu Apr 27 16:45:41 CEST 2023
On 4/18/23 19:46, Jonas Karlman wrote:
> This series fixes eMMC HS400 modes on RK3568 and add support for RK3588.
>
> It has been tested with rock-3a-rk3568/rock5b-rk3588 defconfig and
>
> CONFIG_MMC_HS200_SUPPORT=y
> CONFIG_MMC_HS400_SUPPORT=y
> CONFIG_MMC_HS400_ES_SUPPORT=y
> CONFIG_MMC_SPEED_MODE_SET=y
>
> using the following command to switch mode and then read 512 MiB of data
> from eMMC into memory,
>
> => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000
>
> for each of the modes below.
>
> 0 = MMC legacy
> 1 = MMC High Speed (26MHz)
> 3 = MMC High Speed (52MHz)
> 4 = MMC DDR52 (52MHz)
> 10 = HS200 (200MHz)
> 11 = HS400 (200MHz)
> 12 = HS400ES (200MHz)
>
> All reads have reported OK, prior to this some of these modes worked and
> others failed.
>
> Patch 1-2 fixes an issue with high-speed bit and uhs speed mode field.
> Patch 3-6 refactors the rk3568 driver to use set_clock and config_dll
> ops, so that clocks and regs are changed when output clock is disabled.
> Patch 7-10 continues refactoring and simplification of the driver.
> Patch 11-12 updates tap and delay values to fix HS400 modes on RK3568.
> Patch 13-15 adds support for RK3588 to driver and device tree.
> Patch 16-17 adds workarounds needed to use PIO mode in SPL to
> successfully load TF-A into SRAM when booting from eMMC on RK3588.
>
> Note that this series does not include any change to defconfigs to
> enable HS200/HS400/HS400ES modes.
>
> Changes in v2:
> - Add Signed-off-by tag and update commit message with a note from where
> reg-values originates from
> - Rename quirks to flags
> - Use driver data for hs200/hs400 txclk tapnum values
> - Change u-boot,dm-spl to bootph-pre-ram
>
> This series require working pinctrl, see [1]. A copy of this series and
> its dependencies can be found at [2].
>
> [1] https://patchwork.ozlabs.org/project/uboot/patch/20230315153215.389809-1-eugen.hristev@collabora.com/
> [2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-emmc-v2
>
> Jonas Karlman (16):
> mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz mode
> mmc: sdhci: Set UHS Mode Select field for UHS SDR25 mode
> mmc: rockchip_sdhci: Fix use of device private data
> mmc: rockchip_sdhci: Remove unneeded emmc_phy_init ops
> mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_ops
> mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops
> mmc: rockchip_sdhci: Refactor execute tuning error handling
> mmc: rockchip_sdhci: Update speed mode controls in set_ios_post
> mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe ops
> mmc: rockchip_sdhci: Rearrange and simplify used regs and flags
> mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568
> rockchip: rk3568-rock-3a: Enable support for more eMMC modes
> mmc: rockchip_sdhci: Add support for RK3588
> rockchip: rk3588-rock-5b: Include eMMC node in SPL dtb
> clk: rockchip: rk3588: Add limited TMCLK_EMMC clock support
> mmc: rockchip_sdhci: Limit number of blocks read in a single command
>
> Peter Geis (1):
> mmc: sdhci: Allow disabling of SDMA in SPL
>
> arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 8 +
> arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 12 +-
> arch/arm/dts/rk3588s-u-boot.dtsi | 4 +
> configs/rock5b-rk3588_defconfig | 1 +
> drivers/clk/rockchip/clk_rk3588.c | 2 +
> drivers/mmc/Kconfig | 8 +
> drivers/mmc/rockchip_sdhci.c | 309 +++++++++++++-----------
> drivers/mmc/sdhci.c | 13 +-
> 8 files changed, 215 insertions(+), 142 deletions(-)
>
Hi Jonas,
I saw in the logs you provided in the series that the SPL should also
work in eMMC in rk3588, however, I am getting this error on my rock5b :
Trying to boot from MMC2
spl: mmc boot mode: raw
hdr read sector 4000, count=1
mmc_load_image_raw_sector: mmc block read error
Do you have any idea of what's going wrong ?
Thanks !
Eugen
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