[PATCH v3 02/11] net: dwc_eth_qos: Add StarFive ethernet driver glue layer
Ramon Fried
rfried.dev at gmail.com
Sun Apr 30 21:47:23 CEST 2023
On Fri, Apr 28, 2023 at 5:25 AM Yanhong Wang
<yanhong.wang at starfivetech.com> wrote:
>
> The StarFive ETHQOS hardware has its own clock and reset,so add a
> corresponding glue driver to configure them.
>
> Signed-off-by: Yanhong Wang <yanhong.wang at starfivetech.com>
> ---
> drivers/net/Kconfig | 7 +
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 6 +
> drivers/net/dwc_eth_qos.h | 1 +
> drivers/net/dwc_eth_qos_starfive.c | 249 +++++++++++++++++++++++++++++
> 5 files changed, 264 insertions(+)
> create mode 100644 drivers/net/dwc_eth_qos_starfive.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 09039a283e..5540f0ea18 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -249,6 +249,13 @@ config DWC_ETH_QOS_QCOM
> The Synopsys Designware Ethernet QOS IP block with specific
> configuration used in Qcom QCS404 SoC.
>
> +config DWC_ETH_QOS_STARFIVE
> + bool "Synopsys DWC Ethernet QOS device support for STARFIVE"
> + depends on DWC_ETH_QOS
> + help
> + The Synopsys Designware Ethernet QOS IP block with specific
> + configuration used in STARFIVE JH7110 soc.
> +
> config E1000
> bool "Intel PRO/1000 Gigabit Ethernet support"
> depends on PCI
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 46a40e2ed9..d4af253b6f 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
> obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
> +obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
> obj-$(CONFIG_E1000) += e1000.o
> obj-$(CONFIG_E1000_SPI) += e1000_spi.o
> obj-$(CONFIG_EEPRO100) += eepro100.o
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index ec58697b31..8060a4e782 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1713,6 +1713,12 @@ static const struct udevice_id eqos_ids[] = {
> .data = (ulong)&eqos_qcom_config
> },
> #endif
> +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
> + {
> + .compatible = "starfive,jh7110-dwmac",
> + .data = (ulong)&eqos_jh7110_config
> + },
> +#endif
>
> { }
> };
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index fddbe9336c..a6b719af80 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -289,3 +289,4 @@ int eqos_null_ops(struct udevice *dev);
>
> extern struct eqos_config eqos_imx_config;
> extern struct eqos_config eqos_qcom_config;
> +extern struct eqos_config eqos_jh7110_config;
> diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c
> new file mode 100644
> index 0000000000..5be8ac0f1a
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos_starfive.c
> @@ -0,0 +1,249 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + * Author: Yanhong Wang<yanhong.wang at starfivetech.com>
> + */
> +
> +#include <common.h>
> +#include <asm/cache.h>
> +#include <asm/gpio.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <eth_phy.h>
> +#include <net.h>
> +#include <regmap.h>
> +#include <reset.h>
> +#include <syscon.h>
> +
> +#include "dwc_eth_qos.h"
> +
> +#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
> +#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
> +#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
> +
> +struct starfive_platform_data {
> + struct regmap *regmap;
> + struct reset_ctl_bulk resets;
> + struct clk_bulk clks;
> + phy_interface_t interface;
> + u32 offset;
> + u32 shift;
> + bool tx_use_rgmii_clk;
> +};
> +
> +static int eqos_interface_init_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> + struct ofnode_phandle_args args;
> + unsigned int mode;
> + int ret;
> +
> + switch (data->interface) {
> + case PHY_INTERFACE_MODE_RMII:
> + mode = STARFIVE_DWMAC_PHY_INFT_RMII;
> + break;
> +
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
> + 2, 0, &args);
> + if (ret)
> + return ret;
> +
> + if (args.args_count != 2)
> + return -EINVAL;
> +
> + data->offset = args.args[0];
> + data->shift = args.args[1];
> + data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
> + if (IS_ERR(data->regmap)) {
> + ret = PTR_ERR(data->regmap);
> + pr_err("Failed to get regmap: %d\n", ret);
> + return ret;
> + }
> +
> + return regmap_update_bits(data->regmap, data->offset,
> + STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
> + mode << data->shift);
> +}
> +
> +static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> + struct clk *pclk, *c;
> + ulong rate;
> + int ret;
> +
> + /* Generally, the rgmii_tx clock is provided by the internal clock,
> + * which needs to match the corresponding clock frequency according
> + * to different speeds. If the rgmii_tx clock is provided by the
> + * external rgmii_rxin, there is no need to configure the clock
> + * internally, because rgmii_rxin will be adaptively adjusted.
> + */
> + if (data->tx_use_rgmii_clk)
> + return 0;
> +
> + switch (eqos->phy->speed) {
> + case SPEED_1000:
> + rate = 125 * 1000 * 1000;
> + break;
> + case SPEED_100:
> + rate = 25 * 1000 * 1000;
> + break;
> + case SPEED_10:
> + rate = 2.5 * 1000 * 1000;
> + break;
> + default:
> + pr_err("invalid speed %d", eqos->phy->speed);
> + return -EINVAL;
> + }
> +
> + /* eqos->clk_tx clock has no set rate operation, so just set the parent
> + * clock rate directly
> + */
> + ret = clk_get_by_id(eqos->clk_tx.id, &c);
> + if (ret)
> + return ret;
> +
> + pclk = clk_get_parent(c);
> + if (pclk) {
> + ret = clk_set_rate(pclk, rate);
> + if (ret < 0) {
> + pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> +
> + return clk_get_rate(&eqos->clk_tx);
> +}
> +
> +static int eqos_start_clks_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> +
> + return clk_enable_bulk(&data->clks);
> +}
> +
> +static int eqos_stop_clks_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> +
> + return clk_disable_bulk(&data->clks);
> +}
> +
> +static int eqos_start_resets_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> +
> + return reset_deassert_bulk(&data->resets);
> +}
> +
> +static int eqos_stop_resets_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> +
> + return reset_assert_bulk(&data->resets);
> +}
> +
> +static int eqos_remove_resources_jh7110(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data = pdata->priv_pdata;
> +
> + reset_assert_bulk(&data->resets);
> + clk_disable_bulk(&data->clks);
> +
> + return 0;
> +}
> +
> +static int eqos_probe_resources_jh7110(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct starfive_platform_data *data;
> + int ret;
> +
> + data = calloc(1, sizeof(struct starfive_platform_data));
> + if (!data)
> + return -ENOMEM;
> +
> + pdata->priv_pdata = data;
> + data->interface = eqos->config->interface(dev);
> + if (data->interface == PHY_INTERFACE_MODE_NA) {
> + pr_err("Invalid PHY interface\n");
> + return -EINVAL;
> + }
> +
> + ret = reset_get_bulk(dev, &data->resets);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_get_bulk(dev, &data->clks);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
> + if (ret)
> + return ret;
> +
> + data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");
> +
> + return eqos_interface_init_jh7110(dev);
> +}
> +
> +static struct eqos_ops eqos_jh7110_ops = {
> + .eqos_inval_desc = eqos_inval_desc_generic,
> + .eqos_flush_desc = eqos_flush_desc_generic,
> + .eqos_inval_buffer = eqos_inval_buffer_generic,
> + .eqos_flush_buffer = eqos_flush_buffer_generic,
> + .eqos_probe_resources = eqos_probe_resources_jh7110,
> + .eqos_remove_resources = eqos_remove_resources_jh7110,
> + .eqos_stop_resets = eqos_stop_resets_jh7110,
> + .eqos_start_resets = eqos_start_resets_jh7110,
> + .eqos_stop_clks = eqos_stop_clks_jh7110,
> + .eqos_start_clks = eqos_start_clks_jh7110,
> + .eqos_calibrate_pads = eqos_null_ops,
> + .eqos_disable_calibration = eqos_null_ops,
> + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
> + .eqos_get_enetaddr = eqos_null_ops,
> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
> +};
> +
> +/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
> + * swr_wait: Software reset bit must be read at least 4 CSR clock cycles
> + * after it is written to 1.
> + * config_mac: Enable rx queue to DCB mode.
> + * config_mac_mdio: CSR clock range is 250-300 Mhz.
> + * axi_bus_width: The width of the data bus is 64 bit.
> + */
> +struct eqos_config __maybe_unused eqos_jh7110_config = {
> + .reg_access_always_ok = false,
> + .mdio_wait = 0,
> + .swr_wait = 4,
> + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
> + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
> + .axi_bus_width = EQOS_AXI_WIDTH_64,
> + .interface = dev_read_phy_mode,
> + .ops = &eqos_jh7110_ops
> +};
> --
> 2.17.1
>
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
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