[PATCH 2/5] clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div

[Kever Yang]

On 2023/8/4 17:33, Jonas Karlman wrote:
> The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
> not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
>
> Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
>
> Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 +-
>   drivers/clk/rockchip/clk_rk3568.c               | 5 ++++-
>   2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
> index 399f19ad21ec..2cf590d6d717 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
> @@ -493,7 +493,7 @@ enum {
>   
>   	/* CRU_CLK_SEL81_CON */
>   	CPLL_25M_DIV_SHIFT		= 8,
> -	CPLL_25M_DIV_MASK		= 0x1f << CPLL_25M_DIV_SHIFT,
> +	CPLL_25M_DIV_MASK		= 0x3f << CPLL_25M_DIV_SHIFT,
>   	CPLL_50M_DIV_SHIFT		= 0,
>   	CPLL_50M_DIV_MASK		= 0x1f << CPLL_50M_DIV_SHIFT,
>   
> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
> index e8e4d20e532c..dab254d4d115 100644
> --- a/drivers/clk/rockchip/clk_rk3568.c
> +++ b/drivers/clk/rockchip/clk_rk3568.c
> @@ -702,7 +702,10 @@ static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,
>   	}
>   
>   	div = DIV_ROUND_UP(priv->cpll_hz, rate);
> -	assert(div - 1 <= 31);
> +	if (clk_id == CPLL_25M)
> +		assert(div - 1 <= 63);
> +	else
> +		assert(div - 1 <= 31);
>   	rk_clrsetreg(&cru->clksel_con[con],
>   		     mask, (div - 1) << shift);
>   	return rk3568_cpll_div_get_rate(priv, clk_id);