[PATCH v2 0/3] arch: riscv: jh7110: Correctly zero L2 LIM

[Shengyu Qu]

This series is the second version of Bo Gan's L2 LIM series. Original
author hasn't sent v2 for almost 2 months, so I decided to take over
this series.

Background information:
 JH7110 SPL runs in L2 LIM (2M in size mapped at 0x8000000). It
 consists of 16 0x20000 sized regions, each one can be used as
 either L2 cache way or SRAM (not both). From top to bottom, there're
 ways 0-15. The way 0 is always enabled, at most 0x1e0000 can be used.

In SPL, we don't enable any cache ways, thus all 15 (except way 0)
ways can be used. However, due to HW requirement, we must zero the
LIM before use. This is because ECC is applied to LIM, and if not
cleared first, the ECC part is invalid, which can trigger ECC errors
when reading/writing data.

There are several issues currently. We clear L2 LIM from __bss_end
to 0x81FFFFF in `harts_early_init`. This is wrong because:

 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing `board_init_f_init_reserve`,
    while other harts're in the middle of zeroing L2 LIM.
    (data-race)

Changes since v1:
 - Seperate single patch into several patches

Shengyu Qu (3):
  riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
  riscv: Add ZERO_MEM_BEFORE_USE implementation
  riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE

 arch/riscv/Kconfig            |  8 ++++++++
 arch/riscv/cpu/jh7110/Kconfig |  1 +
 arch/riscv/cpu/jh7110/spl.c   | 25 -------------------------
 arch/riscv/cpu/start.S        | 12 ++++++++++++
 common/init/board_init.c      |  3 +++
 5 files changed, 24 insertions(+), 25 deletions(-)

-- 
2.41.0