[PATCH 0/2] riscv: jh7110: visionfive2: fix u-boot crash due to missing timer

[Torsten Duwe]

Hi all,

Since commit 55171aedda8, U-Boot on the visionfive2 stops at

| initcall sequence 00000000fffd76f8 failed at call 00000000402192c8 (err=-19)
| ### ERROR ### Please RESET the board ###

This is init_sequence_r[initr_dm_devices] calling dm_timer_init, which
returns ENODEV, because the riscv architectural timer got initialised
at the ROM stage, but then discarded at relocation, and never again to
be re-registered. A workaround hack was to allow it to register again
in drivers/core/root.c line 439:

if (CONFIG_IS_ENABLED(DM_EVENT) /* && !(gd->flags & GD_FLG_RELOC) */ ) {

but that would defeat the purpose of the commit 55171aedda8 cleanup.

However, the timer has a defined device tree binding which, when used,
IMHO makes things a lot clearer. AFAIU, the timer roughly corresponds
to the x86 TSC, which is defined on many x86 platforms, compare
yourself:

grep -r tsc_timer.dtsi arch/x86/dts
vs.
grep -r '"riscv,timer"' arch/riscv/dts

At first I tried to create a series that converts all riscv platforms
to use the DT for the CPU timer and removes the calls from the CPU
driver, but this takes too long. Release early, release often -- these
two patches fix the visionfive2, for a start. Others may follow and
the CPU driver calls can be removed later when they are not needed any
longer.

	Torsten

Fixes: 55171aedda8 ("dm: Emit the arch_cpu_init_dm() even only before relocation")
---
Torsten Duwe (2):
  riscv: allow riscv timer to be instantiated via device tree
  riscv: jh7110: enable riscv,timer in the device tree

 arch/riscv/dts/jh7110.dtsi  |  9 +++++++++
 drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++++++++--
 2 files changed, 35 insertions(+), 2 deletions(-)

-- 
2.35.3