[PATCH 6/6] board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev

[Teresa Remmet]

Hello Yannic,

Am Donnerstag, dem 03.08.2023 um 11:09 +0200 schrieb Yannic Moog:
> Hello Teresa,
> 
> On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
> > Starting with PCB revision 3 we can safely make use of higher RAM
> > frequency again. Make use of the EEPROM detection to determine the
> > revision and use the updated RAM timings for new SoMs.
> > 
> > Signed-off-by: Teresa Remmet <t.remmet at phytec.de>
> > ---
> >  board/phytec/phycore_imx8mp/spl.c | 61
> > +++++++++++++++++++++++++++++++
> >  1 file changed, 61 insertions(+)
> > 
> > diff --git a/board/phytec/phycore_imx8mp/spl.c
> > b/board/phytec/phycore_imx8mp/spl.c
> > index e084fe081987..2929c3c50001 100644
> > --- a/board/phytec/phycore_imx8mp/spl.c
> > +++ b/board/phytec/phycore_imx8mp/spl.c
> > @@ -48,6 +48,67 @@ void spl_dram_init(void)
> >  
> >         phytec_print_som_info(NULL);
> >  
> > +       ret = phytec_get_rev(NULL);
> > +       if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
> 
> > +               dram_timing.ddrc_cfg[3].val = 0x1233;
> 
> I believe you swapped to digits here, it should be 0x1323.

argh.. yes. Thanks for the review. I will fix this one and the one
below in v2.

Teresa

> 
> > +               dram_timing.ddrc_cfg[4].val = 0x1e84800;
> > +               dram_timing.ddrc_cfg[5].val = 0x7a0118;
> > +               dram_timing.ddrc_cfg[8].val = 0xc00307a3;
> > +               dram_timing.ddrc_cfg[9].val = 0xc50000;
> > +               dram_timing.ddrc_cfg[10].val = 0xf4003f;
> > +               dram_timing.ddrc_cfg[11].val = 0xf30000;
> > +               dram_timing.ddrc_cfg[14].val = 0x2028222a;
> > +               dram_timing.ddrc_cfg[15].val = 0x8083f;
> > +               dram_timing.ddrc_cfg[16].val = 0xe0e000;
> > +               dram_timing.ddrc_cfg[17].val = 0x12040a12;
> > +               dram_timing.ddrc_cfg[18].val = 0x2050f0f;
> > +               dram_timing.ddrc_cfg[19].val = 0x1010009;
> > +               dram_timing.ddrc_cfg[20].val = 0x502;
> > +               dram_timing.ddrc_cfg[21].val = 0x20800;
> > +               dram_timing.ddrc_cfg[22].val = 0xe100002;
> > +               dram_timing.ddrc_cfg[23].val = 0x120;
> > +               dram_timing.ddrc_cfg[24].val = 0xc80064;
> > +               dram_timing.ddrc_cfg[25].val = 0x3e8001e;
> > +               dram_timing.ddrc_cfg[26].val = 0x3207a12;
> > +               dram_timing.ddrc_cfg[28].val = 0x4a3820e;
> > +               dram_timing.ddrc_cfg[30].val = 0x230e;
> > +               dram_timing.ddrc_cfg[37].val = 0x799;
> > +               dram_timing.ddrc_cfg[38].val = 0x9141d1c;
> > +               dram_timing.ddrc_cfg[74].val = 0x302;
> > +               dram_timing.ddrc_cfg[83].val = 0x599;
> > +               dram_timing.ddrc_cfg[99].val = 0x302;
> > +               dram_timing.ddrc_cfg[108].val = 0x599;
> > +               dram_timing.ddrphy_cfg[66].val = 0x18;
> > +               dram_timing.ddrphy_cfg[75].val = 0x1e3;
> > +               dram_timing.ddrphy_cfg[77].val = 0x1e3;
> > +               dram_timing.ddrphy_cfg[79].val = 0x1e3;
> > +               dram_timing.ddrphy_cfg[145].val = 0x3e8;
> > +               dram_timing.fsp_msg[0].drate = 4000;
> > +               dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
> > +               dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
> > +               dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
> > +               dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
> > +               dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
> > +               dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
> > +               dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
> > +               dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
> > +               dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
> > +               dram_timing.fsp_msg[3].drate = 4000;
> 
> > +               dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xbb8;
> 
> And for this entry, I get 0xfa0.
> 
> Yannic
> 
> > +               dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
> > +               dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
> > +               dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
> > +               dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
> > +               dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
> > +               dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
> > +               dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
> > +               dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
> > +               dram_timing.ddrphy_pie[480].val = 0x465;
> > +               dram_timing.ddrphy_pie[481].val = 0xfa;
> > +               dram_timing.ddrphy_pie[482].val = 0x9c4;
> > +               dram_timing.fsp_table[0] = 4000;
> > +       }
> > +
> >  out:
> >         ddr_init(&dram_timing);
> >  }
> 

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