[PATCH v2 2/5] sunxi: psci: refactor register access to separate functions

Sam Edwards cfsworks at gmail.com
Fri Aug 18 19:32:34 CEST 2023

On 8/18/23 07:57, Andre Przywara wrote:
> On Wed, 16 Aug 2023 10:34:17 -0700
> Sam Edwards <cfsworks at gmail.com> wrote:
> Hi Sam,

Likewise Andre,

>> -static void __secure sunxi_set_entry_address(void *entry)
>> +static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
> So what is the reasoning behind this change?

The primary reason is to be consistent with every other sunxi_cpu_* 
function, while the *tertiary* reason is that it was useful to have that 
argument preserved in a debug build, so that when I was tracing 
execution I could be *sure* that the correct CPU was being chosen (this 
was before I found out that the GIC400 base was being determined 
incorrectly). As for the secondary reason...

> If *none* of the Allwinner SoCs have independent secondary entry point
> registers, we should not give the impression some do in the prototype.
> Should later a SoC emerge that changes this, adjusting this one is the
> least of our problems then.

Ah, but the T113 is already such an SoC. From the user manual:
- The Soft Entry Address Register of CPU0 is 0x070005C4.
- The Soft Entry Address Register of CPU1 is 0x070005C8.

...so my second reason for the function prototype being the way it is 
(and perhaps something which I should be driving home in patch 4/5) is 
indeed to give that impression: that it is *not* the case that none of 
the sunxis have independent secondary entry point registers.

>> +void __secure sunxi_cpu_power_off(u32 cpuid)
> Can you please mark this as static on the way? That does not seem to be
> used anywhere, and even the name suggests it's local.
> Saves 8 bytes of .text ;-)

Easy enough, it shall be done!


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