[PATCH V4 6/8] arm: dts: Add k3-am625-beagleplay
Mattijs Korpershoek
mkorpershoek at baylibre.com
Wed Aug 23 10:26:57 CEST 2023
On mar., août 22, 2023 at 13:41, Nishanth Menon <nm at ti.com> wrote:
> From: Robert Nelson <robertcnelson at gmail.com>
>
> BeagleBoard.org BeaglePlay is an easy to use, affordable open source
> hardware single board computer based on the Texas Instruments AM625
> SoC that allows you to create connected devices that work even at long
> distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L.
> Expansion is provided over open standards based mikroBUS, Grove and
> QWIIC headers among other interfaces.
>
> This board family can be identified by the 24c32 eeprom:
>
> [aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|]
> [50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|]
>
> https://beagleplay.org/
> https://git.beagleboard.org/beagleplay/beagleplay
>
> baseline of base device tree is v6.5-rc1.
>
> Reviewed-by: Tom Rini <trini at konsulko.com>
> Signed-off-by: Robert Nelson <robertcnelson at gmail.com>
> Co-developed-by: Nishanth Menon <nm at ti.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek at baylibre.com>
> ---
> Changes since V3:
> * Added LEDs to u-boot.dtsi boot phase properties and default to be on.
> * Dropped the slowing down of emmc and sd
> * Retaining Tom's reviewed-by unless there is a concern.
>
> V3: https://lore.kernel.org/all/20230815164440.2713726-3-nm@ti.com/
> V2: https://lore.kernel.org/u-boot/20230727234446.3651836-3-nm@ti.com/
> V1: https://lore.kernel.org/all/20230725185253.2123433-5-nm@ti.com/
> arch/arm/dts/Makefile | 2 +
> .../dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi | 2195 +++++++++++++++++
> arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 196 ++
> arch/arm/dts/k3-am625-beagleplay.dts | 758 ++++++
> arch/arm/dts/k3-am625-r5-beagleplay.dts | 87 +
> board/ti/am62x/MAINTAINERS | 7 +
> 6 files changed, 3245 insertions(+)
> create mode 100644 arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi
> create mode 100644 arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-am625-beagleplay.dts
> create mode 100644 arch/arm/dts/k3-am625-r5-beagleplay.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 85fd5b1157b1..bd61a3527082 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1334,6 +1334,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
>
> dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
> k3-am625-r5-sk.dtb \
> + k3-am625-beagleplay.dtb \
> + k3-am625-r5-beagleplay.dtb \
> k3-am625-verdin-wifi-dev.dtb \
> k3-am625-verdin-r5.dtb
>
> diff --git a/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi
> new file mode 100644
> index 000000000000..3d7a41c27d7e
> --- /dev/null
> +++ b/arch/arm/dts/k3-am625-beagleplay-ddr4-1600MTs.dtsi
> @@ -0,0 +1,2195 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * https://beagleboard.org/play
> + *
> + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
> + *
> + * This file was generated with the
> + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.06
> + * Thu Feb 09 2023 11:57:18 GMT-0600 (Central Standard Time)
> + * DDR Part number: K4AAG165WA-BCWE K4A4G165WF-BCTD
> + * DDR Type: DDR4
> + * Frequency = 800MHz (1600MTs)
> + * Density: 16Gb
> + * Number of Ranks: 1
> + */
> +
> +#define DDRSS_PLL_FHS_CNT 6
> +#define DDRSS_PLL_FREQUENCY_1 400000000
> +#define DDRSS_PLL_FREQUENCY_2 400000000
> +
> +#define DDRSS_CTL_0_DATA 0x00000A00
> +#define DDRSS_CTL_1_DATA 0x00000000
> +#define DDRSS_CTL_2_DATA 0x00000000
> +#define DDRSS_CTL_3_DATA 0x00000000
> +#define DDRSS_CTL_4_DATA 0x00000000
> +#define DDRSS_CTL_5_DATA 0x00000000
> +#define DDRSS_CTL_6_DATA 0x00000000
> +#define DDRSS_CTL_7_DATA 0x000890B8
> +#define DDRSS_CTL_8_DATA 0x00000000
> +#define DDRSS_CTL_9_DATA 0x00000000
> +#define DDRSS_CTL_10_DATA 0x00000000
> +#define DDRSS_CTL_11_DATA 0x000890B8
> +#define DDRSS_CTL_12_DATA 0x00000000
> +#define DDRSS_CTL_13_DATA 0x00000000
> +#define DDRSS_CTL_14_DATA 0x00000000
> +#define DDRSS_CTL_15_DATA 0x000890B8
> +#define DDRSS_CTL_16_DATA 0x00000000
> +#define DDRSS_CTL_17_DATA 0x00000000
> +#define DDRSS_CTL_18_DATA 0x00000000
> +#define DDRSS_CTL_19_DATA 0x01010100
> +#define DDRSS_CTL_20_DATA 0x01000100
> +#define DDRSS_CTL_21_DATA 0x01000110
> +#define DDRSS_CTL_22_DATA 0x02010002
> +#define DDRSS_CTL_23_DATA 0x00027100
> +#define DDRSS_CTL_24_DATA 0x00061A80
> +#define DDRSS_CTL_25_DATA 0x04000400
> +#define DDRSS_CTL_26_DATA 0x00000400
> +#define DDRSS_CTL_27_DATA 0x00000000
> +#define DDRSS_CTL_28_DATA 0x00000000
> +#define DDRSS_CTL_29_DATA 0x00000000
> +#define DDRSS_CTL_30_DATA 0x00000000
> +#define DDRSS_CTL_31_DATA 0x00000000
> +#define DDRSS_CTL_32_DATA 0x00000000
> +#define DDRSS_CTL_33_DATA 0x00000000
> +#define DDRSS_CTL_34_DATA 0x00000000
> +#define DDRSS_CTL_35_DATA 0x00000000
> +#define DDRSS_CTL_36_DATA 0x00000000
> +#define DDRSS_CTL_37_DATA 0x00000000
> +#define DDRSS_CTL_38_DATA 0x0400091C
> +#define DDRSS_CTL_39_DATA 0x1C1C1C1C
> +#define DDRSS_CTL_40_DATA 0x0400091C
> +#define DDRSS_CTL_41_DATA 0x1C1C1C1C
> +#define DDRSS_CTL_42_DATA 0x0400091C
> +#define DDRSS_CTL_43_DATA 0x1C1C1C1C
> +#define DDRSS_CTL_44_DATA 0x05050404
> +#define DDRSS_CTL_45_DATA 0x00002706
> +#define DDRSS_CTL_46_DATA 0x0602001D
> +#define DDRSS_CTL_47_DATA 0x05001D0B
> +#define DDRSS_CTL_48_DATA 0x00270605
> +#define DDRSS_CTL_49_DATA 0x0602001D
> +#define DDRSS_CTL_50_DATA 0x05001D0B
> +#define DDRSS_CTL_51_DATA 0x00270605
> +#define DDRSS_CTL_52_DATA 0x0602001D
> +#define DDRSS_CTL_53_DATA 0x07001D0B
> +#define DDRSS_CTL_54_DATA 0x00180807
> +#define DDRSS_CTL_55_DATA 0x0400DB60
> +#define DDRSS_CTL_56_DATA 0x07070009
> +#define DDRSS_CTL_57_DATA 0x00001808
> +#define DDRSS_CTL_58_DATA 0x0400DB60
> +#define DDRSS_CTL_59_DATA 0x07070009
> +#define DDRSS_CTL_60_DATA 0x00001808
> +#define DDRSS_CTL_61_DATA 0x0400DB60
> +#define DDRSS_CTL_62_DATA 0x03000009
> +#define DDRSS_CTL_63_DATA 0x0D0C0002
> +#define DDRSS_CTL_64_DATA 0x0D0C0D0C
> +#define DDRSS_CTL_65_DATA 0x01010000
> +#define DDRSS_CTL_66_DATA 0x03191919
> +#define DDRSS_CTL_67_DATA 0x0B0B0B0B
> +#define DDRSS_CTL_68_DATA 0x00000B0B
> +#define DDRSS_CTL_69_DATA 0x00000101
> +#define DDRSS_CTL_70_DATA 0x00000000
> +#define DDRSS_CTL_71_DATA 0x01000000
> +#define DDRSS_CTL_72_DATA 0x01180803
> +#define DDRSS_CTL_73_DATA 0x00001860
> +#define DDRSS_CTL_74_DATA 0x00000118
> +#define DDRSS_CTL_75_DATA 0x00001860
> +#define DDRSS_CTL_76_DATA 0x00000118
> +#define DDRSS_CTL_77_DATA 0x00001860
> +#define DDRSS_CTL_78_DATA 0x00000005
> +#define DDRSS_CTL_79_DATA 0x00000000
> +#define DDRSS_CTL_80_DATA 0x00000000
> +#define DDRSS_CTL_81_DATA 0x00000000
> +#define DDRSS_CTL_82_DATA 0x00000000
> +#define DDRSS_CTL_83_DATA 0x00000000
> +#define DDRSS_CTL_84_DATA 0x00000000
> +#define DDRSS_CTL_85_DATA 0x00000000
> +#define DDRSS_CTL_86_DATA 0x00000000
> +#define DDRSS_CTL_87_DATA 0x00090009
> +#define DDRSS_CTL_88_DATA 0x00000009
> +#define DDRSS_CTL_89_DATA 0x00000000
> +#define DDRSS_CTL_90_DATA 0x00000000
> +#define DDRSS_CTL_91_DATA 0x00000000
> +#define DDRSS_CTL_92_DATA 0x00000000
> +#define DDRSS_CTL_93_DATA 0x00000000
> +#define DDRSS_CTL_94_DATA 0x00010001
> +#define DDRSS_CTL_95_DATA 0x00040001
> +#define DDRSS_CTL_96_DATA 0x04000120
> +#define DDRSS_CTL_97_DATA 0x04000120
> +#define DDRSS_CTL_98_DATA 0x01200120
> +#define DDRSS_CTL_99_DATA 0x01200120
> +#define DDRSS_CTL_100_DATA 0x00000000
> +#define DDRSS_CTL_101_DATA 0x00000000
> +#define DDRSS_CTL_102_DATA 0x00000000
> +#define DDRSS_CTL_103_DATA 0x00000000
> +#define DDRSS_CTL_104_DATA 0x00000000
> +#define DDRSS_CTL_105_DATA 0x00000000
> +#define DDRSS_CTL_106_DATA 0x03010000
> +#define DDRSS_CTL_107_DATA 0x00010000
> +#define DDRSS_CTL_108_DATA 0x00000000
> +#define DDRSS_CTL_109_DATA 0x01000000
> +#define DDRSS_CTL_110_DATA 0x80104002
> +#define DDRSS_CTL_111_DATA 0x00040003
> +#define DDRSS_CTL_112_DATA 0x00040005
> +#define DDRSS_CTL_113_DATA 0x00030000
> +#define DDRSS_CTL_114_DATA 0x00050004
> +#define DDRSS_CTL_115_DATA 0x00000004
> +#define DDRSS_CTL_116_DATA 0x00040003
> +#define DDRSS_CTL_117_DATA 0x00040005
> +#define DDRSS_CTL_118_DATA 0x00000000
> +#define DDRSS_CTL_119_DATA 0x00061800
> +#define DDRSS_CTL_120_DATA 0x00061800
> +#define DDRSS_CTL_121_DATA 0x00061800
> +#define DDRSS_CTL_122_DATA 0x00061800
> +#define DDRSS_CTL_123_DATA 0x00061800
> +#define DDRSS_CTL_124_DATA 0x00000000
> +#define DDRSS_CTL_125_DATA 0x0000AAA0
> +#define DDRSS_CTL_126_DATA 0x00061800
> +#define DDRSS_CTL_127_DATA 0x00061800
> +#define DDRSS_CTL_128_DATA 0x00061800
> +#define DDRSS_CTL_129_DATA 0x00061800
> +#define DDRSS_CTL_130_DATA 0x00061800
> +#define DDRSS_CTL_131_DATA 0x00000000
> +#define DDRSS_CTL_132_DATA 0x0000AAA0
> +#define DDRSS_CTL_133_DATA 0x00061800
> +#define DDRSS_CTL_134_DATA 0x00061800
> +#define DDRSS_CTL_135_DATA 0x00061800
> +#define DDRSS_CTL_136_DATA 0x00061800
> +#define DDRSS_CTL_137_DATA 0x00061800
> +#define DDRSS_CTL_138_DATA 0x00000000
> +#define DDRSS_CTL_139_DATA 0x0000AAA0
> +#define DDRSS_CTL_140_DATA 0x00000000
> +#define DDRSS_CTL_141_DATA 0x00000000
> +#define DDRSS_CTL_142_DATA 0x00000000
> +#define DDRSS_CTL_143_DATA 0x00000000
> +#define DDRSS_CTL_144_DATA 0x00000000
> +#define DDRSS_CTL_145_DATA 0x00000000
> +#define DDRSS_CTL_146_DATA 0x00000000
> +#define DDRSS_CTL_147_DATA 0x00000000
> +#define DDRSS_CTL_148_DATA 0x00000000
> +#define DDRSS_CTL_149_DATA 0x00000000
> +#define DDRSS_CTL_150_DATA 0x00000000
> +#define DDRSS_CTL_151_DATA 0x00000000
> +#define DDRSS_CTL_152_DATA 0x00000000
> +#define DDRSS_CTL_153_DATA 0x00000000
> +#define DDRSS_CTL_154_DATA 0x00000000
> +#define DDRSS_CTL_155_DATA 0x00000000
> +#define DDRSS_CTL_156_DATA 0x080C0000
> +#define DDRSS_CTL_157_DATA 0x080C080C
> +#define DDRSS_CTL_158_DATA 0x08000000
> +#define DDRSS_CTL_159_DATA 0x00000808
> +#define DDRSS_CTL_160_DATA 0x000E0000
> +#define DDRSS_CTL_161_DATA 0x00080808
> +#define DDRSS_CTL_162_DATA 0x0E000000
> +#define DDRSS_CTL_163_DATA 0x08080800
> +#define DDRSS_CTL_164_DATA 0x00000000
> +#define DDRSS_CTL_165_DATA 0x0000080E
> +#define DDRSS_CTL_166_DATA 0x00040003
> +#define DDRSS_CTL_167_DATA 0x00000007
> +#define DDRSS_CTL_168_DATA 0x00000000
> +#define DDRSS_CTL_169_DATA 0x00000000
> +#define DDRSS_CTL_170_DATA 0x00000000
> +#define DDRSS_CTL_171_DATA 0x00000000
> +#define DDRSS_CTL_172_DATA 0x00000000
> +#define DDRSS_CTL_173_DATA 0x00000000
> +#define DDRSS_CTL_174_DATA 0x01000000
> +#define DDRSS_CTL_175_DATA 0x00000000
> +#define DDRSS_CTL_176_DATA 0x00001500
> +#define DDRSS_CTL_177_DATA 0x0000100E
> +#define DDRSS_CTL_178_DATA 0x00000000
> +#define DDRSS_CTL_179_DATA 0x00000000
> +#define DDRSS_CTL_180_DATA 0x00000001
> +#define DDRSS_CTL_181_DATA 0x00000002
> +#define DDRSS_CTL_182_DATA 0x00000C00
> +#define DDRSS_CTL_183_DATA 0x00001000
> +#define DDRSS_CTL_184_DATA 0x00000C00
> +#define DDRSS_CTL_185_DATA 0x00001000
> +#define DDRSS_CTL_186_DATA 0x00000C00
> +#define DDRSS_CTL_187_DATA 0x00001000
> +#define DDRSS_CTL_188_DATA 0x00000000
> +#define DDRSS_CTL_189_DATA 0x00000000
> +#define DDRSS_CTL_190_DATA 0x00000000
> +#define DDRSS_CTL_191_DATA 0x00000000
> +#define DDRSS_CTL_192_DATA 0x00000000
> +#define DDRSS_CTL_193_DATA 0x00000000
> +#define DDRSS_CTL_194_DATA 0x00000000
> +#define DDRSS_CTL_195_DATA 0x00000000
> +#define DDRSS_CTL_196_DATA 0x00000000
> +#define DDRSS_CTL_197_DATA 0x00000000
> +#define DDRSS_CTL_198_DATA 0x00000000
> +#define DDRSS_CTL_199_DATA 0x00000000
> +#define DDRSS_CTL_200_DATA 0x00000000
> +#define DDRSS_CTL_201_DATA 0x00000000
> +#define DDRSS_CTL_202_DATA 0x00000000
> +#define DDRSS_CTL_203_DATA 0x00000000
> +#define DDRSS_CTL_204_DATA 0x00042400
> +#define DDRSS_CTL_205_DATA 0x00000301
> +#define DDRSS_CTL_206_DATA 0x00000000
> +#define DDRSS_CTL_207_DATA 0x00000424
> +#define DDRSS_CTL_208_DATA 0x00000301
> +#define DDRSS_CTL_209_DATA 0x00000000
> +#define DDRSS_CTL_210_DATA 0x00000424
> +#define DDRSS_CTL_211_DATA 0x00000301
> +#define DDRSS_CTL_212_DATA 0x00000000
> +#define DDRSS_CTL_213_DATA 0x00000424
> +#define DDRSS_CTL_214_DATA 0x00000301
> +#define DDRSS_CTL_215_DATA 0x00000000
> +#define DDRSS_CTL_216_DATA 0x00000424
> +#define DDRSS_CTL_217_DATA 0x00000301
> +#define DDRSS_CTL_218_DATA 0x00000000
> +#define DDRSS_CTL_219_DATA 0x00000424
> +#define DDRSS_CTL_220_DATA 0x00000301
> +#define DDRSS_CTL_221_DATA 0x00000000
> +#define DDRSS_CTL_222_DATA 0x00000000
> +#define DDRSS_CTL_223_DATA 0x00000000
> +#define DDRSS_CTL_224_DATA 0x00000000
> +#define DDRSS_CTL_225_DATA 0x00000000
> +#define DDRSS_CTL_226_DATA 0x00000000
> +#define DDRSS_CTL_227_DATA 0x00000000
> +#define DDRSS_CTL_228_DATA 0x00000000
> +#define DDRSS_CTL_229_DATA 0x00000000
> +#define DDRSS_CTL_230_DATA 0x00000000
> +#define DDRSS_CTL_231_DATA 0x00000000
> +#define DDRSS_CTL_232_DATA 0x00000000
> +#define DDRSS_CTL_233_DATA 0x00000000
> +#define DDRSS_CTL_234_DATA 0x00000000
> +#define DDRSS_CTL_235_DATA 0x00000000
> +#define DDRSS_CTL_236_DATA 0x00001401
> +#define DDRSS_CTL_237_DATA 0x00001401
> +#define DDRSS_CTL_238_DATA 0x00001401
> +#define DDRSS_CTL_239_DATA 0x00001401
> +#define DDRSS_CTL_240_DATA 0x00001401
> +#define DDRSS_CTL_241_DATA 0x00001401
> +#define DDRSS_CTL_242_DATA 0x00000493
> +#define DDRSS_CTL_243_DATA 0x00000493
> +#define DDRSS_CTL_244_DATA 0x00000493
> +#define DDRSS_CTL_245_DATA 0x00000493
> +#define DDRSS_CTL_246_DATA 0x00000493
> +#define DDRSS_CTL_247_DATA 0x00000493
> +#define DDRSS_CTL_248_DATA 0x00000000
> +#define DDRSS_CTL_249_DATA 0x00000000
> +#define DDRSS_CTL_250_DATA 0x00000000
> +#define DDRSS_CTL_251_DATA 0x00000000
> +#define DDRSS_CTL_252_DATA 0x00000000
> +#define DDRSS_CTL_253_DATA 0x00000000
> +#define DDRSS_CTL_254_DATA 0x00000000
> +#define DDRSS_CTL_255_DATA 0x00000000
> +#define DDRSS_CTL_256_DATA 0x00000000
> +#define DDRSS_CTL_257_DATA 0x00000000
> +#define DDRSS_CTL_258_DATA 0x00000000
> +#define DDRSS_CTL_259_DATA 0x00000000
> +#define DDRSS_CTL_260_DATA 0x00000000
> +#define DDRSS_CTL_261_DATA 0x00000000
> +#define DDRSS_CTL_262_DATA 0x00000000
> +#define DDRSS_CTL_263_DATA 0x00000000
> +#define DDRSS_CTL_264_DATA 0x00000000
> +#define DDRSS_CTL_265_DATA 0x00000000
> +#define DDRSS_CTL_266_DATA 0x00000000
> +#define DDRSS_CTL_267_DATA 0x00000000
> +#define DDRSS_CTL_268_DATA 0x00000000
> +#define DDRSS_CTL_269_DATA 0x00000000
> +#define DDRSS_CTL_270_DATA 0x00000000
> +#define DDRSS_CTL_271_DATA 0x00000000
> +#define DDRSS_CTL_272_DATA 0x00000000
> +#define DDRSS_CTL_273_DATA 0x00000000
> +#define DDRSS_CTL_274_DATA 0x00000000
> +#define DDRSS_CTL_275_DATA 0x00000000
> +#define DDRSS_CTL_276_DATA 0x00000000
> +#define DDRSS_CTL_277_DATA 0x00010000
> +#define DDRSS_CTL_278_DATA 0x00000000
> +#define DDRSS_CTL_279_DATA 0x00000000
> +#define DDRSS_CTL_280_DATA 0x00000000
> +#define DDRSS_CTL_281_DATA 0x00000101
> +#define DDRSS_CTL_282_DATA 0x00000000
> +#define DDRSS_CTL_283_DATA 0x00000000
> +#define DDRSS_CTL_284_DATA 0x00000000
> +#define DDRSS_CTL_285_DATA 0x00000000
> +#define DDRSS_CTL_286_DATA 0x00000000
> +#define DDRSS_CTL_287_DATA 0x00000000
> +#define DDRSS_CTL_288_DATA 0x00000000
> +#define DDRSS_CTL_289_DATA 0x00000000
> +#define DDRSS_CTL_290_DATA 0x0C181511
> +#define DDRSS_CTL_291_DATA 0x00000304
> +#define DDRSS_CTL_292_DATA 0x00000000
> +#define DDRSS_CTL_293_DATA 0x00000000
> +#define DDRSS_CTL_294_DATA 0x00000000
> +#define DDRSS_CTL_295_DATA 0x00000000
> +#define DDRSS_CTL_296_DATA 0x00000000
> +#define DDRSS_CTL_297_DATA 0x00000000
> +#define DDRSS_CTL_298_DATA 0x00000000
> +#define DDRSS_CTL_299_DATA 0x00000000
> +#define DDRSS_CTL_300_DATA 0x00000000
> +#define DDRSS_CTL_301_DATA 0x00000000
> +#define DDRSS_CTL_302_DATA 0x00000000
> +#define DDRSS_CTL_303_DATA 0x00000000
> +#define DDRSS_CTL_304_DATA 0x00000000
> +#define DDRSS_CTL_305_DATA 0x00040000
> +#define DDRSS_CTL_306_DATA 0x00800200
> +#define DDRSS_CTL_307_DATA 0x00000000
> +#define DDRSS_CTL_308_DATA 0x02000400
> +#define DDRSS_CTL_309_DATA 0x00000080
> +#define DDRSS_CTL_310_DATA 0x00040000
> +#define DDRSS_CTL_311_DATA 0x00800200
> +#define DDRSS_CTL_312_DATA 0x00000000
> +#define DDRSS_CTL_313_DATA 0x00000000
> +#define DDRSS_CTL_314_DATA 0x00000000
> +#define DDRSS_CTL_315_DATA 0x00000100
> +#define DDRSS_CTL_316_DATA 0x01010000
> +#define DDRSS_CTL_317_DATA 0x00000000
> +#define DDRSS_CTL_318_DATA 0x3FFF0000
> +#define DDRSS_CTL_319_DATA 0x000FFF00
> +#define DDRSS_CTL_320_DATA 0xFFFFFFFF
> +#define DDRSS_CTL_321_DATA 0x00FFFF00
> +#define DDRSS_CTL_322_DATA 0x0A000000
> +#define DDRSS_CTL_323_DATA 0x0001FFFF
> +#define DDRSS_CTL_324_DATA 0x01010101
> +#define DDRSS_CTL_325_DATA 0x01010101
> +#define DDRSS_CTL_326_DATA 0x00000118
> +#define DDRSS_CTL_327_DATA 0x00000C01
> +#define DDRSS_CTL_328_DATA 0x00000000
> +#define DDRSS_CTL_329_DATA 0x00000000
> +#define DDRSS_CTL_330_DATA 0x00000000
> +#define DDRSS_CTL_331_DATA 0x01000000
> +#define DDRSS_CTL_332_DATA 0x00000100
> +#define DDRSS_CTL_333_DATA 0x00010000
> +#define DDRSS_CTL_334_DATA 0x00000000
> +#define DDRSS_CTL_335_DATA 0x00000000
> +#define DDRSS_CTL_336_DATA 0x00000000
> +#define DDRSS_CTL_337_DATA 0x00000000
> +#define DDRSS_CTL_338_DATA 0x00000000
> +#define DDRSS_CTL_339_DATA 0x00000000
> +#define DDRSS_CTL_340_DATA 0x00000000
> +#define DDRSS_CTL_341_DATA 0x00000000
> +#define DDRSS_CTL_342_DATA 0x00000000
> +#define DDRSS_CTL_343_DATA 0x00000000
> +#define DDRSS_CTL_344_DATA 0x00000000
> +#define DDRSS_CTL_345_DATA 0x00000000
> +#define DDRSS_CTL_346_DATA 0x00000000
> +#define DDRSS_CTL_347_DATA 0x00000000
> +#define DDRSS_CTL_348_DATA 0x00000000
> +#define DDRSS_CTL_349_DATA 0x00000000
> +#define DDRSS_CTL_350_DATA 0x00000000
> +#define DDRSS_CTL_351_DATA 0x00000000
> +#define DDRSS_CTL_352_DATA 0x00000000
> +#define DDRSS_CTL_353_DATA 0x00000000
> +#define DDRSS_CTL_354_DATA 0x00000000
> +#define DDRSS_CTL_355_DATA 0x00000000
> +#define DDRSS_CTL_356_DATA 0x00000000
> +#define DDRSS_CTL_357_DATA 0x00000000
> +#define DDRSS_CTL_358_DATA 0x00000000
> +#define DDRSS_CTL_359_DATA 0x00000000
> +#define DDRSS_CTL_360_DATA 0x00000000
> +#define DDRSS_CTL_361_DATA 0x00000000
> +#define DDRSS_CTL_362_DATA 0x00000000
> +#define DDRSS_CTL_363_DATA 0x00000000
> +#define DDRSS_CTL_364_DATA 0x00000000
> +#define DDRSS_CTL_365_DATA 0x00000000
> +#define DDRSS_CTL_366_DATA 0x00000000
> +#define DDRSS_CTL_367_DATA 0x00000000
> +#define DDRSS_CTL_368_DATA 0x00000000
> +#define DDRSS_CTL_369_DATA 0x00000000
> +#define DDRSS_CTL_370_DATA 0x0C000000
> +#define DDRSS_CTL_371_DATA 0x060C0606
> +#define DDRSS_CTL_372_DATA 0x06060C06
> +#define DDRSS_CTL_373_DATA 0x00010101
> +#define DDRSS_CTL_374_DATA 0x02000000
> +#define DDRSS_CTL_375_DATA 0x05020101
> +#define DDRSS_CTL_376_DATA 0x00000505
> +#define DDRSS_CTL_377_DATA 0x02020200
> +#define DDRSS_CTL_378_DATA 0x02020202
> +#define DDRSS_CTL_379_DATA 0x02020202
> +#define DDRSS_CTL_380_DATA 0x02020202
> +#define DDRSS_CTL_381_DATA 0x00000000
> +#define DDRSS_CTL_382_DATA 0x00000000
> +#define DDRSS_CTL_383_DATA 0x04000100
> +#define DDRSS_CTL_384_DATA 0x1E000004
> +#define DDRSS_CTL_385_DATA 0x000030C0
> +#define DDRSS_CTL_386_DATA 0x00000200
> +#define DDRSS_CTL_387_DATA 0x00000200
> +#define DDRSS_CTL_388_DATA 0x00000200
> +#define DDRSS_CTL_389_DATA 0x00000200
> +#define DDRSS_CTL_390_DATA 0x0000DB60
> +#define DDRSS_CTL_391_DATA 0x0001E780
> +#define DDRSS_CTL_392_DATA 0x0C0D0302
> +#define DDRSS_CTL_393_DATA 0x001E090A
> +#define DDRSS_CTL_394_DATA 0x000030C0
> +#define DDRSS_CTL_395_DATA 0x00000200
> +#define DDRSS_CTL_396_DATA 0x00000200
> +#define DDRSS_CTL_397_DATA 0x00000200
> +#define DDRSS_CTL_398_DATA 0x00000200
> +#define DDRSS_CTL_399_DATA 0x0000DB60
> +#define DDRSS_CTL_400_DATA 0x0001E780
> +#define DDRSS_CTL_401_DATA 0x0C0D0302
> +#define DDRSS_CTL_402_DATA 0x001E090A
> +#define DDRSS_CTL_403_DATA 0x000030C0
> +#define DDRSS_CTL_404_DATA 0x00000200
> +#define DDRSS_CTL_405_DATA 0x00000200
> +#define DDRSS_CTL_406_DATA 0x00000200
> +#define DDRSS_CTL_407_DATA 0x00000200
> +#define DDRSS_CTL_408_DATA 0x0000DB60
> +#define DDRSS_CTL_409_DATA 0x0001E780
> +#define DDRSS_CTL_410_DATA 0x0C0D0302
> +#define DDRSS_CTL_411_DATA 0x0000090A
> +#define DDRSS_CTL_412_DATA 0x00000000
> +#define DDRSS_CTL_413_DATA 0x0302000A
> +#define DDRSS_CTL_414_DATA 0x01000500
> +#define DDRSS_CTL_415_DATA 0x01010001
> +#define DDRSS_CTL_416_DATA 0x00010001
> +#define DDRSS_CTL_417_DATA 0x01010001
> +#define DDRSS_CTL_418_DATA 0x02010000
> +#define DDRSS_CTL_419_DATA 0x00000200
> +#define DDRSS_CTL_420_DATA 0x02000201
> +#define DDRSS_CTL_421_DATA 0x00000000
> +#define DDRSS_CTL_422_DATA 0x00202020
> +#define DDRSS_PI_0_DATA 0x00000A00
> +#define DDRSS_PI_1_DATA 0x00000000
> +#define DDRSS_PI_2_DATA 0x00000000
> +#define DDRSS_PI_3_DATA 0x01000000
> +#define DDRSS_PI_4_DATA 0x00000001
> +#define DDRSS_PI_5_DATA 0x00010064
> +#define DDRSS_PI_6_DATA 0x00000000
> +#define DDRSS_PI_7_DATA 0x00000000
> +#define DDRSS_PI_8_DATA 0x00000000
> +#define DDRSS_PI_9_DATA 0x00000000
> +#define DDRSS_PI_10_DATA 0x00000000
> +#define DDRSS_PI_11_DATA 0x00000000
> +#define DDRSS_PI_12_DATA 0x00000000
> +#define DDRSS_PI_13_DATA 0x00010001
> +#define DDRSS_PI_14_DATA 0x00000000
> +#define DDRSS_PI_15_DATA 0x00010001
> +#define DDRSS_PI_16_DATA 0x00000005
> +#define DDRSS_PI_17_DATA 0x00000000
> +#define DDRSS_PI_18_DATA 0x00000000
> +#define DDRSS_PI_19_DATA 0x00000000
> +#define DDRSS_PI_20_DATA 0x00000000
> +#define DDRSS_PI_21_DATA 0x00000000
> +#define DDRSS_PI_22_DATA 0x00000000
> +#define DDRSS_PI_23_DATA 0x00000000
> +#define DDRSS_PI_24_DATA 0x280D0001
> +#define DDRSS_PI_25_DATA 0x00000000
> +#define DDRSS_PI_26_DATA 0x00010000
> +#define DDRSS_PI_27_DATA 0x00003200
> +#define DDRSS_PI_28_DATA 0x00000000
> +#define DDRSS_PI_29_DATA 0x00000000
> +#define DDRSS_PI_30_DATA 0x00060602
> +#define DDRSS_PI_31_DATA 0x00000000
> +#define DDRSS_PI_32_DATA 0x00000000
> +#define DDRSS_PI_33_DATA 0x00000000
> +#define DDRSS_PI_34_DATA 0x00000001
> +#define DDRSS_PI_35_DATA 0x00000055
> +#define DDRSS_PI_36_DATA 0x000000AA
> +#define DDRSS_PI_37_DATA 0x000000AD
> +#define DDRSS_PI_38_DATA 0x00000052
> +#define DDRSS_PI_39_DATA 0x0000006A
> +#define DDRSS_PI_40_DATA 0x00000095
> +#define DDRSS_PI_41_DATA 0x00000095
> +#define DDRSS_PI_42_DATA 0x000000AD
> +#define DDRSS_PI_43_DATA 0x00000000
> +#define DDRSS_PI_44_DATA 0x00000000
> +#define DDRSS_PI_45_DATA 0x00010100
> +#define DDRSS_PI_46_DATA 0x00000014
> +#define DDRSS_PI_47_DATA 0x000007D0
> +#define DDRSS_PI_48_DATA 0x00000300
> +#define DDRSS_PI_49_DATA 0x00000000
> +#define DDRSS_PI_50_DATA 0x00000000
> +#define DDRSS_PI_51_DATA 0x01000000
> +#define DDRSS_PI_52_DATA 0x00010101
> +#define DDRSS_PI_53_DATA 0x01000000
> +#define DDRSS_PI_54_DATA 0x00000000
> +#define DDRSS_PI_55_DATA 0x00010000
> +#define DDRSS_PI_56_DATA 0x00000000
> +#define DDRSS_PI_57_DATA 0x00000000
> +#define DDRSS_PI_58_DATA 0x00000000
> +#define DDRSS_PI_59_DATA 0x00000000
> +#define DDRSS_PI_60_DATA 0x00001400
> +#define DDRSS_PI_61_DATA 0x00000000
> +#define DDRSS_PI_62_DATA 0x01000000
> +#define DDRSS_PI_63_DATA 0x00000404
> +#define DDRSS_PI_64_DATA 0x00000001
> +#define DDRSS_PI_65_DATA 0x0001010E
> +#define DDRSS_PI_66_DATA 0x02040100
> +#define DDRSS_PI_67_DATA 0x00010000
> +#define DDRSS_PI_68_DATA 0x00000034
> +#define DDRSS_PI_69_DATA 0x00000000
> +#define DDRSS_PI_70_DATA 0x00000000
> +#define DDRSS_PI_71_DATA 0x00000000
> +#define DDRSS_PI_72_DATA 0x00000000
> +#define DDRSS_PI_73_DATA 0x00000000
> +#define DDRSS_PI_74_DATA 0x00000000
> +#define DDRSS_PI_75_DATA 0x00000005
> +#define DDRSS_PI_76_DATA 0x01000000
> +#define DDRSS_PI_77_DATA 0x04000100
> +#define DDRSS_PI_78_DATA 0x00020000
> +#define DDRSS_PI_79_DATA 0x00010002
> +#define DDRSS_PI_80_DATA 0x00000001
> +#define DDRSS_PI_81_DATA 0x00020001
> +#define DDRSS_PI_82_DATA 0x00020002
> +#define DDRSS_PI_83_DATA 0x00000000
> +#define DDRSS_PI_84_DATA 0x00000000
> +#define DDRSS_PI_85_DATA 0x00000000
> +#define DDRSS_PI_86_DATA 0x00000000
> +#define DDRSS_PI_87_DATA 0x00000000
> +#define DDRSS_PI_88_DATA 0x00000000
> +#define DDRSS_PI_89_DATA 0x00000000
> +#define DDRSS_PI_90_DATA 0x00000000
> +#define DDRSS_PI_91_DATA 0x00000300
> +#define DDRSS_PI_92_DATA 0x0A090B0C
> +#define DDRSS_PI_93_DATA 0x04060708
> +#define DDRSS_PI_94_DATA 0x01000005
> +#define DDRSS_PI_95_DATA 0x00000800
> +#define DDRSS_PI_96_DATA 0x00000000
> +#define DDRSS_PI_97_DATA 0x00010008
> +#define DDRSS_PI_98_DATA 0x00000000
> +#define DDRSS_PI_99_DATA 0x0000AA00
> +#define DDRSS_PI_100_DATA 0x00000000
> +#define DDRSS_PI_101_DATA 0x00010000
> +#define DDRSS_PI_102_DATA 0x00000000
> +#define DDRSS_PI_103_DATA 0x00000000
> +#define DDRSS_PI_104_DATA 0x00000000
> +#define DDRSS_PI_105_DATA 0x00000000
> +#define DDRSS_PI_106_DATA 0x00000000
> +#define DDRSS_PI_107_DATA 0x00000000
> +#define DDRSS_PI_108_DATA 0x00000000
> +#define DDRSS_PI_109_DATA 0x00000000
> +#define DDRSS_PI_110_DATA 0x00000000
> +#define DDRSS_PI_111_DATA 0x00000000
> +#define DDRSS_PI_112_DATA 0x00000000
> +#define DDRSS_PI_113_DATA 0x00000000
> +#define DDRSS_PI_114_DATA 0x00000000
> +#define DDRSS_PI_115_DATA 0x00000000
> +#define DDRSS_PI_116_DATA 0x00000000
> +#define DDRSS_PI_117_DATA 0x00000000
> +#define DDRSS_PI_118_DATA 0x00000000
> +#define DDRSS_PI_119_DATA 0x00000000
> +#define DDRSS_PI_120_DATA 0x00000000
> +#define DDRSS_PI_121_DATA 0x00000000
> +#define DDRSS_PI_122_DATA 0x00000000
> +#define DDRSS_PI_123_DATA 0x00000000
> +#define DDRSS_PI_124_DATA 0x00000008
> +#define DDRSS_PI_125_DATA 0x00000000
> +#define DDRSS_PI_126_DATA 0x00000000
> +#define DDRSS_PI_127_DATA 0x00000000
> +#define DDRSS_PI_128_DATA 0x00000000
> +#define DDRSS_PI_129_DATA 0x00000000
> +#define DDRSS_PI_130_DATA 0x00000000
> +#define DDRSS_PI_131_DATA 0x00000000
> +#define DDRSS_PI_132_DATA 0x00000000
> +#define DDRSS_PI_133_DATA 0x00010100
> +#define DDRSS_PI_134_DATA 0x00000000
> +#define DDRSS_PI_135_DATA 0x00000000
> +#define DDRSS_PI_136_DATA 0x00027100
> +#define DDRSS_PI_137_DATA 0x00061A80
> +#define DDRSS_PI_138_DATA 0x00000100
> +#define DDRSS_PI_139_DATA 0x00000000
> +#define DDRSS_PI_140_DATA 0x00000000
> +#define DDRSS_PI_141_DATA 0x00000000
> +#define DDRSS_PI_142_DATA 0x00000000
> +#define DDRSS_PI_143_DATA 0x00000000
> +#define DDRSS_PI_144_DATA 0x01000000
> +#define DDRSS_PI_145_DATA 0x00010003
> +#define DDRSS_PI_146_DATA 0x02000101
> +#define DDRSS_PI_147_DATA 0x01030001
> +#define DDRSS_PI_148_DATA 0x00010400
> +#define DDRSS_PI_149_DATA 0x06000105
> +#define DDRSS_PI_150_DATA 0x01070001
> +#define DDRSS_PI_151_DATA 0x00000000
> +#define DDRSS_PI_152_DATA 0x00000000
> +#define DDRSS_PI_153_DATA 0x00000000
> +#define DDRSS_PI_154_DATA 0x00010000
> +#define DDRSS_PI_155_DATA 0x00000000
> +#define DDRSS_PI_156_DATA 0x00000000
> +#define DDRSS_PI_157_DATA 0x00000000
> +#define DDRSS_PI_158_DATA 0x00000000
> +#define DDRSS_PI_159_DATA 0x00010000
> +#define DDRSS_PI_160_DATA 0x00000004
> +#define DDRSS_PI_161_DATA 0x00000000
> +#define DDRSS_PI_162_DATA 0x00000000
> +#define DDRSS_PI_163_DATA 0x00000000
> +#define DDRSS_PI_164_DATA 0x00007800
> +#define DDRSS_PI_165_DATA 0x00780078
> +#define DDRSS_PI_166_DATA 0x00141414
> +#define DDRSS_PI_167_DATA 0x0000003A
> +#define DDRSS_PI_168_DATA 0x0000003A
> +#define DDRSS_PI_169_DATA 0x0004003A
> +#define DDRSS_PI_170_DATA 0x04000400
> +#define DDRSS_PI_171_DATA 0xC8040009
> +#define DDRSS_PI_172_DATA 0x0400091C
> +#define DDRSS_PI_173_DATA 0x00091CC8
> +#define DDRSS_PI_174_DATA 0x001CC804
> +#define DDRSS_PI_175_DATA 0x00000118
> +#define DDRSS_PI_176_DATA 0x00001860
> +#define DDRSS_PI_177_DATA 0x00000118
> +#define DDRSS_PI_178_DATA 0x00001860
> +#define DDRSS_PI_179_DATA 0x00000118
> +#define DDRSS_PI_180_DATA 0x04001860
> +#define DDRSS_PI_181_DATA 0x01010404
> +#define DDRSS_PI_182_DATA 0x00001901
> +#define DDRSS_PI_183_DATA 0x00190019
> +#define DDRSS_PI_184_DATA 0x010C010C
> +#define DDRSS_PI_185_DATA 0x0000010C
> +#define DDRSS_PI_186_DATA 0x00000000
> +#define DDRSS_PI_187_DATA 0x05000000
> +#define DDRSS_PI_188_DATA 0x01010505
> +#define DDRSS_PI_189_DATA 0x01010101
> +#define DDRSS_PI_190_DATA 0x00181818
> +#define DDRSS_PI_191_DATA 0x00000000
> +#define DDRSS_PI_192_DATA 0x00000000
> +#define DDRSS_PI_193_DATA 0x0D000000
> +#define DDRSS_PI_194_DATA 0x0A0A0D0D
> +#define DDRSS_PI_195_DATA 0x0303030A
> +#define DDRSS_PI_196_DATA 0x00000000
> +#define DDRSS_PI_197_DATA 0x00000000
> +#define DDRSS_PI_198_DATA 0x00000000
> +#define DDRSS_PI_199_DATA 0x00000000
> +#define DDRSS_PI_200_DATA 0x00000000
> +#define DDRSS_PI_201_DATA 0x00000000
> +#define DDRSS_PI_202_DATA 0x00000000
> +#define DDRSS_PI_203_DATA 0x00000000
> +#define DDRSS_PI_204_DATA 0x00000000
> +#define DDRSS_PI_205_DATA 0x00000000
> +#define DDRSS_PI_206_DATA 0x00000000
> +#define DDRSS_PI_207_DATA 0x00000000
> +#define DDRSS_PI_208_DATA 0x00000000
> +#define DDRSS_PI_209_DATA 0x0D090000
> +#define DDRSS_PI_210_DATA 0x0D09000D
> +#define DDRSS_PI_211_DATA 0x0D09000D
> +#define DDRSS_PI_212_DATA 0x0000000D
> +#define DDRSS_PI_213_DATA 0x00000000
> +#define DDRSS_PI_214_DATA 0x00000000
> +#define DDRSS_PI_215_DATA 0x00000000
> +#define DDRSS_PI_216_DATA 0x00000000
> +#define DDRSS_PI_217_DATA 0x16000000
> +#define DDRSS_PI_218_DATA 0x001600C8
> +#define DDRSS_PI_219_DATA 0x001600C8
> +#define DDRSS_PI_220_DATA 0x010100C8
> +#define DDRSS_PI_221_DATA 0x00001B01
> +#define DDRSS_PI_222_DATA 0x1F0F0053
> +#define DDRSS_PI_223_DATA 0x05000001
> +#define DDRSS_PI_224_DATA 0x001B0A0D
> +#define DDRSS_PI_225_DATA 0x1F0F0053
> +#define DDRSS_PI_226_DATA 0x05000001
> +#define DDRSS_PI_227_DATA 0x001B0A0D
> +#define DDRSS_PI_228_DATA 0x1F0F0053
> +#define DDRSS_PI_229_DATA 0x05000001
> +#define DDRSS_PI_230_DATA 0x00010A0D
> +#define DDRSS_PI_231_DATA 0x0C0B0700
> +#define DDRSS_PI_232_DATA 0x000D0605
> +#define DDRSS_PI_233_DATA 0x0000C570
> +#define DDRSS_PI_234_DATA 0x0000001D
> +#define DDRSS_PI_235_DATA 0x180A0800
> +#define DDRSS_PI_236_DATA 0x0B071C1C
> +#define DDRSS_PI_237_DATA 0x0D06050C
> +#define DDRSS_PI_238_DATA 0x0000C570
> +#define DDRSS_PI_239_DATA 0x0000001D
> +#define DDRSS_PI_240_DATA 0x180A0800
> +#define DDRSS_PI_241_DATA 0x0B071C1C
> +#define DDRSS_PI_242_DATA 0x0D06050C
> +#define DDRSS_PI_243_DATA 0x0000C570
> +#define DDRSS_PI_244_DATA 0x0000001D
> +#define DDRSS_PI_245_DATA 0x180A0800
> +#define DDRSS_PI_246_DATA 0x00001C1C
> +#define DDRSS_PI_247_DATA 0x000030C0
> +#define DDRSS_PI_248_DATA 0x0001E780
> +#define DDRSS_PI_249_DATA 0x000030C0
> +#define DDRSS_PI_250_DATA 0x0001E780
> +#define DDRSS_PI_251_DATA 0x000030C0
> +#define DDRSS_PI_252_DATA 0x0001E780
> +#define DDRSS_PI_253_DATA 0x04000400
> +#define DDRSS_PI_254_DATA 0x03030400
> +#define DDRSS_PI_255_DATA 0x00040003
> +#define DDRSS_PI_256_DATA 0x04000400
> +#define DDRSS_PI_257_DATA 0x0C080C08
> +#define DDRSS_PI_258_DATA 0x00000C08
> +#define DDRSS_PI_259_DATA 0x000890B8
> +#define DDRSS_PI_260_DATA 0x00000000
> +#define DDRSS_PI_261_DATA 0x00000000
> +#define DDRSS_PI_262_DATA 0x00000000
> +#define DDRSS_PI_263_DATA 0x00000120
> +#define DDRSS_PI_264_DATA 0x000890B8
> +#define DDRSS_PI_265_DATA 0x00000000
> +#define DDRSS_PI_266_DATA 0x00000000
> +#define DDRSS_PI_267_DATA 0x00000000
> +#define DDRSS_PI_268_DATA 0x00000120
> +#define DDRSS_PI_269_DATA 0x000890B8
> +#define DDRSS_PI_270_DATA 0x00000000
> +#define DDRSS_PI_271_DATA 0x00000000
> +#define DDRSS_PI_272_DATA 0x00000000
> +#define DDRSS_PI_273_DATA 0x02000120
> +#define DDRSS_PI_274_DATA 0x00000080
> +#define DDRSS_PI_275_DATA 0x00020000
> +#define DDRSS_PI_276_DATA 0x00000080
> +#define DDRSS_PI_277_DATA 0x00020000
> +#define DDRSS_PI_278_DATA 0x00000080
> +#define DDRSS_PI_279_DATA 0x00000000
> +#define DDRSS_PI_280_DATA 0x00000000
> +#define DDRSS_PI_281_DATA 0x00040404
> +#define DDRSS_PI_282_DATA 0x00000000
> +#define DDRSS_PI_283_DATA 0x02010102
> +#define DDRSS_PI_284_DATA 0x67676767
> +#define DDRSS_PI_285_DATA 0x00000202
> +#define DDRSS_PI_286_DATA 0x00000000
> +#define DDRSS_PI_287_DATA 0x00000000
> +#define DDRSS_PI_288_DATA 0x00000000
> +#define DDRSS_PI_289_DATA 0x00000000
> +#define DDRSS_PI_290_DATA 0x00000000
> +#define DDRSS_PI_291_DATA 0x0D100F00
> +#define DDRSS_PI_292_DATA 0x0003020E
> +#define DDRSS_PI_293_DATA 0x00000001
> +#define DDRSS_PI_294_DATA 0x01000000
> +#define DDRSS_PI_295_DATA 0x00020201
> +#define DDRSS_PI_296_DATA 0x00000000
> +#define DDRSS_PI_297_DATA 0x00000424
> +#define DDRSS_PI_298_DATA 0x00000301
> +#define DDRSS_PI_299_DATA 0x00000000
> +#define DDRSS_PI_300_DATA 0x00000000
> +#define DDRSS_PI_301_DATA 0x00000000
> +#define DDRSS_PI_302_DATA 0x00001401
> +#define DDRSS_PI_303_DATA 0x00000493
> +#define DDRSS_PI_304_DATA 0x00000000
> +#define DDRSS_PI_305_DATA 0x00000424
> +#define DDRSS_PI_306_DATA 0x00000301
> +#define DDRSS_PI_307_DATA 0x00000000
> +#define DDRSS_PI_308_DATA 0x00000000
> +#define DDRSS_PI_309_DATA 0x00000000
> +#define DDRSS_PI_310_DATA 0x00001401
> +#define DDRSS_PI_311_DATA 0x00000493
> +#define DDRSS_PI_312_DATA 0x00000000
> +#define DDRSS_PI_313_DATA 0x00000424
> +#define DDRSS_PI_314_DATA 0x00000301
> +#define DDRSS_PI_315_DATA 0x00000000
> +#define DDRSS_PI_316_DATA 0x00000000
> +#define DDRSS_PI_317_DATA 0x00000000
> +#define DDRSS_PI_318_DATA 0x00001401
> +#define DDRSS_PI_319_DATA 0x00000493
> +#define DDRSS_PI_320_DATA 0x00000000
> +#define DDRSS_PI_321_DATA 0x00000424
> +#define DDRSS_PI_322_DATA 0x00000301
> +#define DDRSS_PI_323_DATA 0x00000000
> +#define DDRSS_PI_324_DATA 0x00000000
> +#define DDRSS_PI_325_DATA 0x00000000
> +#define DDRSS_PI_326_DATA 0x00001401
> +#define DDRSS_PI_327_DATA 0x00000493
> +#define DDRSS_PI_328_DATA 0x00000000
> +#define DDRSS_PI_329_DATA 0x00000424
> +#define DDRSS_PI_330_DATA 0x00000301
> +#define DDRSS_PI_331_DATA 0x00000000
> +#define DDRSS_PI_332_DATA 0x00000000
> +#define DDRSS_PI_333_DATA 0x00000000
> +#define DDRSS_PI_334_DATA 0x00001401
> +#define DDRSS_PI_335_DATA 0x00000493
> +#define DDRSS_PI_336_DATA 0x00000000
> +#define DDRSS_PI_337_DATA 0x00000424
> +#define DDRSS_PI_338_DATA 0x00000301
> +#define DDRSS_PI_339_DATA 0x00000000
> +#define DDRSS_PI_340_DATA 0x00000000
> +#define DDRSS_PI_341_DATA 0x00000000
> +#define DDRSS_PI_342_DATA 0x00001401
> +#define DDRSS_PI_343_DATA 0x00000493
> +#define DDRSS_PI_344_DATA 0x00000000
> +#define DDRSS_PHY_0_DATA 0x04C00000
> +#define DDRSS_PHY_1_DATA 0x00000000
> +#define DDRSS_PHY_2_DATA 0x00000200
> +#define DDRSS_PHY_3_DATA 0x00000000
> +#define DDRSS_PHY_4_DATA 0x00000000
> +#define DDRSS_PHY_5_DATA 0x00000000
> +#define DDRSS_PHY_6_DATA 0x00000000
> +#define DDRSS_PHY_7_DATA 0x00000000
> +#define DDRSS_PHY_8_DATA 0x00000001
> +#define DDRSS_PHY_9_DATA 0x00000000
> +#define DDRSS_PHY_10_DATA 0x00000000
> +#define DDRSS_PHY_11_DATA 0x010101FF
> +#define DDRSS_PHY_12_DATA 0x00010000
> +#define DDRSS_PHY_13_DATA 0x00C00004
> +#define DDRSS_PHY_14_DATA 0x00CC0008
> +#define DDRSS_PHY_15_DATA 0x00660201
> +#define DDRSS_PHY_16_DATA 0x00000000
> +#define DDRSS_PHY_17_DATA 0x00000000
> +#define DDRSS_PHY_18_DATA 0x00000000
> +#define DDRSS_PHY_19_DATA 0x0000AAAA
> +#define DDRSS_PHY_20_DATA 0x00005555
> +#define DDRSS_PHY_21_DATA 0x0000B5B5
> +#define DDRSS_PHY_22_DATA 0x00004A4A
> +#define DDRSS_PHY_23_DATA 0x00005656
> +#define DDRSS_PHY_24_DATA 0x0000A9A9
> +#define DDRSS_PHY_25_DATA 0x0000B7B7
> +#define DDRSS_PHY_26_DATA 0x00004848
> +#define DDRSS_PHY_27_DATA 0x00000000
> +#define DDRSS_PHY_28_DATA 0x00000000
> +#define DDRSS_PHY_29_DATA 0x08000000
> +#define DDRSS_PHY_30_DATA 0x0F000008
> +#define DDRSS_PHY_31_DATA 0x00000F0F
> +#define DDRSS_PHY_32_DATA 0x00E4E400
> +#define DDRSS_PHY_33_DATA 0x00070820
> +#define DDRSS_PHY_34_DATA 0x000C0020
> +#define DDRSS_PHY_35_DATA 0x00062000
> +#define DDRSS_PHY_36_DATA 0x00000000
> +#define DDRSS_PHY_37_DATA 0x55555555
> +#define DDRSS_PHY_38_DATA 0xAAAAAAAA
> +#define DDRSS_PHY_39_DATA 0x55555555
> +#define DDRSS_PHY_40_DATA 0xAAAAAAAA
> +#define DDRSS_PHY_41_DATA 0x00005555
> +#define DDRSS_PHY_42_DATA 0x01000100
> +#define DDRSS_PHY_43_DATA 0x00800180
> +#define DDRSS_PHY_44_DATA 0x00000000
> +#define DDRSS_PHY_45_DATA 0x00000000
> +#define DDRSS_PHY_46_DATA 0x00000000
> +#define DDRSS_PHY_47_DATA 0x00000000
> +#define DDRSS_PHY_48_DATA 0x00000000
> +#define DDRSS_PHY_49_DATA 0x00000000
> +#define DDRSS_PHY_50_DATA 0x00000000
> +#define DDRSS_PHY_51_DATA 0x00000000
> +#define DDRSS_PHY_52_DATA 0x00000000
> +#define DDRSS_PHY_53_DATA 0x00000000
> +#define DDRSS_PHY_54_DATA 0x00000000
> +#define DDRSS_PHY_55_DATA 0x00000000
> +#define DDRSS_PHY_56_DATA 0x00000000
> +#define DDRSS_PHY_57_DATA 0x00000000
> +#define DDRSS_PHY_58_DATA 0x00000000
> +#define DDRSS_PHY_59_DATA 0x00000000
> +#define DDRSS_PHY_60_DATA 0x00000000
> +#define DDRSS_PHY_61_DATA 0x00000000
> +#define DDRSS_PHY_62_DATA 0x00000000
> +#define DDRSS_PHY_63_DATA 0x00000000
> +#define DDRSS_PHY_64_DATA 0x00000000
> +#define DDRSS_PHY_65_DATA 0x00000004
> +#define DDRSS_PHY_66_DATA 0x00000000
> +#define DDRSS_PHY_67_DATA 0x00000000
> +#define DDRSS_PHY_68_DATA 0x00000000
> +#define DDRSS_PHY_69_DATA 0x00000000
> +#define DDRSS_PHY_70_DATA 0x00000000
> +#define DDRSS_PHY_71_DATA 0x00000000
> +#define DDRSS_PHY_72_DATA 0x041F07FF
> +#define DDRSS_PHY_73_DATA 0x00000000
> +#define DDRSS_PHY_74_DATA 0x01CCB001
> +#define DDRSS_PHY_75_DATA 0x2000CCB0
> +#define DDRSS_PHY_76_DATA 0x20000140
> +#define DDRSS_PHY_77_DATA 0x07FF0200
> +#define DDRSS_PHY_78_DATA 0x0000DD01
> +#define DDRSS_PHY_79_DATA 0x10100303
> +#define DDRSS_PHY_80_DATA 0x10101010
> +#define DDRSS_PHY_81_DATA 0x10101010
> +#define DDRSS_PHY_82_DATA 0x00021010
> +#define DDRSS_PHY_83_DATA 0x00100010
> +#define DDRSS_PHY_84_DATA 0x00100010
> +#define DDRSS_PHY_85_DATA 0x00100010
> +#define DDRSS_PHY_86_DATA 0x00100010
> +#define DDRSS_PHY_87_DATA 0x02020010
> +#define DDRSS_PHY_88_DATA 0x51515041
> +#define DDRSS_PHY_89_DATA 0x31804000
> +#define DDRSS_PHY_90_DATA 0x04BF0340
> +#define DDRSS_PHY_91_DATA 0x01008080
> +#define DDRSS_PHY_92_DATA 0x04050001
> +#define DDRSS_PHY_93_DATA 0x00000504
> +#define DDRSS_PHY_94_DATA 0x42100010
> +#define DDRSS_PHY_95_DATA 0x010C053E
> +#define DDRSS_PHY_96_DATA 0x000F0C14
> +#define DDRSS_PHY_97_DATA 0x01000140
> +#define DDRSS_PHY_98_DATA 0x007A0120
> +#define DDRSS_PHY_99_DATA 0x00000C00
> +#define DDRSS_PHY_100_DATA 0x000001CC
> +#define DDRSS_PHY_101_DATA 0x20100200
> +#define DDRSS_PHY_102_DATA 0x00000005
> +#define DDRSS_PHY_103_DATA 0x76543210
> +#define DDRSS_PHY_104_DATA 0x00000008
> +#define DDRSS_PHY_105_DATA 0x02800280
> +#define DDRSS_PHY_106_DATA 0x02800280
> +#define DDRSS_PHY_107_DATA 0x02800280
> +#define DDRSS_PHY_108_DATA 0x02800280
> +#define DDRSS_PHY_109_DATA 0x00000280
> +#define DDRSS_PHY_110_DATA 0x00008000
> +#define DDRSS_PHY_111_DATA 0x00800080
> +#define DDRSS_PHY_112_DATA 0x00800080
> +#define DDRSS_PHY_113_DATA 0x00800080
> +#define DDRSS_PHY_114_DATA 0x00800080
> +#define DDRSS_PHY_115_DATA 0x00800080
> +#define DDRSS_PHY_116_DATA 0x00800080
> +#define DDRSS_PHY_117_DATA 0x00800080
> +#define DDRSS_PHY_118_DATA 0x00800080
> +#define DDRSS_PHY_119_DATA 0x01000080
> +#define DDRSS_PHY_120_DATA 0x01000000
> +#define DDRSS_PHY_121_DATA 0x00000000
> +#define DDRSS_PHY_122_DATA 0x00000000
> +#define DDRSS_PHY_123_DATA 0x00080200
> +#define DDRSS_PHY_124_DATA 0x00000000
> +#define DDRSS_PHY_125_DATA 0x00000000
> +#define DDRSS_PHY_126_DATA 0x00000000
> +#define DDRSS_PHY_127_DATA 0x00000000
> +#define DDRSS_PHY_128_DATA 0x00000000
> +#define DDRSS_PHY_129_DATA 0x00000000
> +#define DDRSS_PHY_130_DATA 0x00000000
> +#define DDRSS_PHY_131_DATA 0x00000000
> +#define DDRSS_PHY_132_DATA 0x00000000
> +#define DDRSS_PHY_133_DATA 0x00000000
> +#define DDRSS_PHY_134_DATA 0x00000000
> +#define DDRSS_PHY_135_DATA 0x00000000
> +#define DDRSS_PHY_136_DATA 0x00000000
> +#define DDRSS_PHY_137_DATA 0x00000000
> +#define DDRSS_PHY_138_DATA 0x00000000
> +#define DDRSS_PHY_139_DATA 0x00000000
> +#define DDRSS_PHY_140_DATA 0x00000000
> +#define DDRSS_PHY_141_DATA 0x00000000
> +#define DDRSS_PHY_142_DATA 0x00000000
> +#define DDRSS_PHY_143_DATA 0x00000000
> +#define DDRSS_PHY_144_DATA 0x00000000
> +#define DDRSS_PHY_145_DATA 0x00000000
> +#define DDRSS_PHY_146_DATA 0x00000000
> +#define DDRSS_PHY_147_DATA 0x00000000
> +#define DDRSS_PHY_148_DATA 0x00000000
> +#define DDRSS_PHY_149_DATA 0x00000000
> +#define DDRSS_PHY_150_DATA 0x00000000
> +#define DDRSS_PHY_151_DATA 0x00000000
> +#define DDRSS_PHY_152_DATA 0x00000000
> +#define DDRSS_PHY_153_DATA 0x00000000
> +#define DDRSS_PHY_154_DATA 0x00000000
> +#define DDRSS_PHY_155_DATA 0x00000000
> +#define DDRSS_PHY_156_DATA 0x00000000
> +#define DDRSS_PHY_157_DATA 0x00000000
> +#define DDRSS_PHY_158_DATA 0x00000000
> +#define DDRSS_PHY_159_DATA 0x00000000
> +#define DDRSS_PHY_160_DATA 0x00000000
> +#define DDRSS_PHY_161_DATA 0x00000000
> +#define DDRSS_PHY_162_DATA 0x00000000
> +#define DDRSS_PHY_163_DATA 0x00000000
> +#define DDRSS_PHY_164_DATA 0x00000000
> +#define DDRSS_PHY_165_DATA 0x00000000
> +#define DDRSS_PHY_166_DATA 0x00000000
> +#define DDRSS_PHY_167_DATA 0x00000000
> +#define DDRSS_PHY_168_DATA 0x00000000
> +#define DDRSS_PHY_169_DATA 0x00000000
> +#define DDRSS_PHY_170_DATA 0x00000000
> +#define DDRSS_PHY_171_DATA 0x00000000
> +#define DDRSS_PHY_172_DATA 0x00000000
> +#define DDRSS_PHY_173_DATA 0x00000000
> +#define DDRSS_PHY_174_DATA 0x00000000
> +#define DDRSS_PHY_175_DATA 0x00000000
> +#define DDRSS_PHY_176_DATA 0x00000000
> +#define DDRSS_PHY_177_DATA 0x00000000
> +#define DDRSS_PHY_178_DATA 0x00000000
> +#define DDRSS_PHY_179_DATA 0x00000000
> +#define DDRSS_PHY_180_DATA 0x00000000
> +#define DDRSS_PHY_181_DATA 0x00000000
> +#define DDRSS_PHY_182_DATA 0x00000000
> +#define DDRSS_PHY_183_DATA 0x00000000
> +#define DDRSS_PHY_184_DATA 0x00000000
> +#define DDRSS_PHY_185_DATA 0x00000000
> +#define DDRSS_PHY_186_DATA 0x00000000
> +#define DDRSS_PHY_187_DATA 0x00000000
> +#define DDRSS_PHY_188_DATA 0x00000000
> +#define DDRSS_PHY_189_DATA 0x00000000
> +#define DDRSS_PHY_190_DATA 0x00000000
> +#define DDRSS_PHY_191_DATA 0x00000000
> +#define DDRSS_PHY_192_DATA 0x00000000
> +#define DDRSS_PHY_193_DATA 0x00000000
> +#define DDRSS_PHY_194_DATA 0x00000000
> +#define DDRSS_PHY_195_DATA 0x00000000
> +#define DDRSS_PHY_196_DATA 0x00000000
> +#define DDRSS_PHY_197_DATA 0x00000000
> +#define DDRSS_PHY_198_DATA 0x00000000
> +#define DDRSS_PHY_199_DATA 0x00000000
> +#define DDRSS_PHY_200_DATA 0x00000000
> +#define DDRSS_PHY_201_DATA 0x00000000
> +#define DDRSS_PHY_202_DATA 0x00000000
> +#define DDRSS_PHY_203_DATA 0x00000000
> +#define DDRSS_PHY_204_DATA 0x00000000
> +#define DDRSS_PHY_205_DATA 0x00000000
> +#define DDRSS_PHY_206_DATA 0x00000000
> +#define DDRSS_PHY_207_DATA 0x00000000
> +#define DDRSS_PHY_208_DATA 0x00000000
> +#define DDRSS_PHY_209_DATA 0x00000000
> +#define DDRSS_PHY_210_DATA 0x00000000
> +#define DDRSS_PHY_211_DATA 0x00000000
> +#define DDRSS_PHY_212_DATA 0x00000000
> +#define DDRSS_PHY_213_DATA 0x00000000
> +#define DDRSS_PHY_214_DATA 0x00000000
> +#define DDRSS_PHY_215_DATA 0x00000000
> +#define DDRSS_PHY_216_DATA 0x00000000
> +#define DDRSS_PHY_217_DATA 0x00000000
> +#define DDRSS_PHY_218_DATA 0x00000000
> +#define DDRSS_PHY_219_DATA 0x00000000
> +#define DDRSS_PHY_220_DATA 0x00000000
> +#define DDRSS_PHY_221_DATA 0x00000000
> +#define DDRSS_PHY_222_DATA 0x00000000
> +#define DDRSS_PHY_223_DATA 0x00000000
> +#define DDRSS_PHY_224_DATA 0x00000000
> +#define DDRSS_PHY_225_DATA 0x00000000
> +#define DDRSS_PHY_226_DATA 0x00000000
> +#define DDRSS_PHY_227_DATA 0x00000000
> +#define DDRSS_PHY_228_DATA 0x00000000
> +#define DDRSS_PHY_229_DATA 0x00000000
> +#define DDRSS_PHY_230_DATA 0x00000000
> +#define DDRSS_PHY_231_DATA 0x00000000
> +#define DDRSS_PHY_232_DATA 0x00000000
> +#define DDRSS_PHY_233_DATA 0x00000000
> +#define DDRSS_PHY_234_DATA 0x00000000
> +#define DDRSS_PHY_235_DATA 0x00000000
> +#define DDRSS_PHY_236_DATA 0x00000000
> +#define DDRSS_PHY_237_DATA 0x00000000
> +#define DDRSS_PHY_238_DATA 0x00000000
> +#define DDRSS_PHY_239_DATA 0x00000000
> +#define DDRSS_PHY_240_DATA 0x00000000
> +#define DDRSS_PHY_241_DATA 0x00000000
> +#define DDRSS_PHY_242_DATA 0x00000000
> +#define DDRSS_PHY_243_DATA 0x00000000
> +#define DDRSS_PHY_244_DATA 0x00000000
> +#define DDRSS_PHY_245_DATA 0x00000000
> +#define DDRSS_PHY_246_DATA 0x00000000
> +#define DDRSS_PHY_247_DATA 0x00000000
> +#define DDRSS_PHY_248_DATA 0x00000000
> +#define DDRSS_PHY_249_DATA 0x00000000
> +#define DDRSS_PHY_250_DATA 0x00000000
> +#define DDRSS_PHY_251_DATA 0x00000000
> +#define DDRSS_PHY_252_DATA 0x00000000
> +#define DDRSS_PHY_253_DATA 0x00000000
> +#define DDRSS_PHY_254_DATA 0x00000000
> +#define DDRSS_PHY_255_DATA 0x00000000
> +#define DDRSS_PHY_256_DATA 0x04C00000
> +#define DDRSS_PHY_257_DATA 0x00000000
> +#define DDRSS_PHY_258_DATA 0x00000200
> +#define DDRSS_PHY_259_DATA 0x00000000
> +#define DDRSS_PHY_260_DATA 0x00000000
> +#define DDRSS_PHY_261_DATA 0x00000000
> +#define DDRSS_PHY_262_DATA 0x00000000
> +#define DDRSS_PHY_263_DATA 0x00000000
> +#define DDRSS_PHY_264_DATA 0x00000001
> +#define DDRSS_PHY_265_DATA 0x00000000
> +#define DDRSS_PHY_266_DATA 0x00000000
> +#define DDRSS_PHY_267_DATA 0x010101FF
> +#define DDRSS_PHY_268_DATA 0x00010000
> +#define DDRSS_PHY_269_DATA 0x00C00004
> +#define DDRSS_PHY_270_DATA 0x00CC0008
> +#define DDRSS_PHY_271_DATA 0x00660201
> +#define DDRSS_PHY_272_DATA 0x00000000
> +#define DDRSS_PHY_273_DATA 0x00000000
> +#define DDRSS_PHY_274_DATA 0x00000000
> +#define DDRSS_PHY_275_DATA 0x0000AAAA
> +#define DDRSS_PHY_276_DATA 0x00005555
> +#define DDRSS_PHY_277_DATA 0x0000B5B5
> +#define DDRSS_PHY_278_DATA 0x00004A4A
> +#define DDRSS_PHY_279_DATA 0x00005656
> +#define DDRSS_PHY_280_DATA 0x0000A9A9
> +#define DDRSS_PHY_281_DATA 0x0000B7B7
> +#define DDRSS_PHY_282_DATA 0x00004848
> +#define DDRSS_PHY_283_DATA 0x00000000
> +#define DDRSS_PHY_284_DATA 0x00000000
> +#define DDRSS_PHY_285_DATA 0x08000000
> +#define DDRSS_PHY_286_DATA 0x0F000008
> +#define DDRSS_PHY_287_DATA 0x00000F0F
> +#define DDRSS_PHY_288_DATA 0x00E4E400
> +#define DDRSS_PHY_289_DATA 0x00070820
> +#define DDRSS_PHY_290_DATA 0x000C0020
> +#define DDRSS_PHY_291_DATA 0x00062000
> +#define DDRSS_PHY_292_DATA 0x00000000
> +#define DDRSS_PHY_293_DATA 0x55555555
> +#define DDRSS_PHY_294_DATA 0xAAAAAAAA
> +#define DDRSS_PHY_295_DATA 0x55555555
> +#define DDRSS_PHY_296_DATA 0xAAAAAAAA
> +#define DDRSS_PHY_297_DATA 0x00005555
> +#define DDRSS_PHY_298_DATA 0x01000100
> +#define DDRSS_PHY_299_DATA 0x00800180
> +#define DDRSS_PHY_300_DATA 0x00000000
> +#define DDRSS_PHY_301_DATA 0x00000000
> +#define DDRSS_PHY_302_DATA 0x00000000
> +#define DDRSS_PHY_303_DATA 0x00000000
> +#define DDRSS_PHY_304_DATA 0x00000000
> +#define DDRSS_PHY_305_DATA 0x00000000
> +#define DDRSS_PHY_306_DATA 0x00000000
> +#define DDRSS_PHY_307_DATA 0x00000000
> +#define DDRSS_PHY_308_DATA 0x00000000
> +#define DDRSS_PHY_309_DATA 0x00000000
> +#define DDRSS_PHY_310_DATA 0x00000000
> +#define DDRSS_PHY_311_DATA 0x00000000
> +#define DDRSS_PHY_312_DATA 0x00000000
> +#define DDRSS_PHY_313_DATA 0x00000000
> +#define DDRSS_PHY_314_DATA 0x00000000
> +#define DDRSS_PHY_315_DATA 0x00000000
> +#define DDRSS_PHY_316_DATA 0x00000000
> +#define DDRSS_PHY_317_DATA 0x00000000
> +#define DDRSS_PHY_318_DATA 0x00000000
> +#define DDRSS_PHY_319_DATA 0x00000000
> +#define DDRSS_PHY_320_DATA 0x00000000
> +#define DDRSS_PHY_321_DATA 0x00000004
> +#define DDRSS_PHY_322_DATA 0x00000000
> +#define DDRSS_PHY_323_DATA 0x00000000
> +#define DDRSS_PHY_324_DATA 0x00000000
> +#define DDRSS_PHY_325_DATA 0x00000000
> +#define DDRSS_PHY_326_DATA 0x00000000
> +#define DDRSS_PHY_327_DATA 0x00000000
> +#define DDRSS_PHY_328_DATA 0x041F07FF
> +#define DDRSS_PHY_329_DATA 0x00000000
> +#define DDRSS_PHY_330_DATA 0x01CCB001
> +#define DDRSS_PHY_331_DATA 0x2000CCB0
> +#define DDRSS_PHY_332_DATA 0x20000140
> +#define DDRSS_PHY_333_DATA 0x07FF0200
> +#define DDRSS_PHY_334_DATA 0x0000DD01
> +#define DDRSS_PHY_335_DATA 0x10100303
> +#define DDRSS_PHY_336_DATA 0x10101010
> +#define DDRSS_PHY_337_DATA 0x10101010
> +#define DDRSS_PHY_338_DATA 0x00021010
> +#define DDRSS_PHY_339_DATA 0x00100010
> +#define DDRSS_PHY_340_DATA 0x00100010
> +#define DDRSS_PHY_341_DATA 0x00100010
> +#define DDRSS_PHY_342_DATA 0x00100010
> +#define DDRSS_PHY_343_DATA 0x02020010
> +#define DDRSS_PHY_344_DATA 0x51515041
> +#define DDRSS_PHY_345_DATA 0x31804000
> +#define DDRSS_PHY_346_DATA 0x04BF0340
> +#define DDRSS_PHY_347_DATA 0x01008080
> +#define DDRSS_PHY_348_DATA 0x04050001
> +#define DDRSS_PHY_349_DATA 0x00000504
> +#define DDRSS_PHY_350_DATA 0x42100010
> +#define DDRSS_PHY_351_DATA 0x010C053E
> +#define DDRSS_PHY_352_DATA 0x000F0C14
> +#define DDRSS_PHY_353_DATA 0x01000140
> +#define DDRSS_PHY_354_DATA 0x007A0120
> +#define DDRSS_PHY_355_DATA 0x00000C00
> +#define DDRSS_PHY_356_DATA 0x000001CC
> +#define DDRSS_PHY_357_DATA 0x20100200
> +#define DDRSS_PHY_358_DATA 0x00000005
> +#define DDRSS_PHY_359_DATA 0x76543210
> +#define DDRSS_PHY_360_DATA 0x00000008
> +#define DDRSS_PHY_361_DATA 0x02800280
> +#define DDRSS_PHY_362_DATA 0x02800280
> +#define DDRSS_PHY_363_DATA 0x02800280
> +#define DDRSS_PHY_364_DATA 0x02800280
> +#define DDRSS_PHY_365_DATA 0x00000280
> +#define DDRSS_PHY_366_DATA 0x00008000
> +#define DDRSS_PHY_367_DATA 0x00800080
> +#define DDRSS_PHY_368_DATA 0x00800080
> +#define DDRSS_PHY_369_DATA 0x00800080
> +#define DDRSS_PHY_370_DATA 0x00800080
> +#define DDRSS_PHY_371_DATA 0x00800080
> +#define DDRSS_PHY_372_DATA 0x00800080
> +#define DDRSS_PHY_373_DATA 0x00800080
> +#define DDRSS_PHY_374_DATA 0x00800080
> +#define DDRSS_PHY_375_DATA 0x01000080
> +#define DDRSS_PHY_376_DATA 0x01000000
> +#define DDRSS_PHY_377_DATA 0x00000000
> +#define DDRSS_PHY_378_DATA 0x00000000
> +#define DDRSS_PHY_379_DATA 0x00080200
> +#define DDRSS_PHY_380_DATA 0x00000000
> +#define DDRSS_PHY_381_DATA 0x00000000
> +#define DDRSS_PHY_382_DATA 0x00000000
> +#define DDRSS_PHY_383_DATA 0x00000000
> +#define DDRSS_PHY_384_DATA 0x00000000
> +#define DDRSS_PHY_385_DATA 0x00000000
> +#define DDRSS_PHY_386_DATA 0x00000000
> +#define DDRSS_PHY_387_DATA 0x00000000
> +#define DDRSS_PHY_388_DATA 0x00000000
> +#define DDRSS_PHY_389_DATA 0x00000000
> +#define DDRSS_PHY_390_DATA 0x00000000
> +#define DDRSS_PHY_391_DATA 0x00000000
> +#define DDRSS_PHY_392_DATA 0x00000000
> +#define DDRSS_PHY_393_DATA 0x00000000
> +#define DDRSS_PHY_394_DATA 0x00000000
> +#define DDRSS_PHY_395_DATA 0x00000000
> +#define DDRSS_PHY_396_DATA 0x00000000
> +#define DDRSS_PHY_397_DATA 0x00000000
> +#define DDRSS_PHY_398_DATA 0x00000000
> +#define DDRSS_PHY_399_DATA 0x00000000
> +#define DDRSS_PHY_400_DATA 0x00000000
> +#define DDRSS_PHY_401_DATA 0x00000000
> +#define DDRSS_PHY_402_DATA 0x00000000
> +#define DDRSS_PHY_403_DATA 0x00000000
> +#define DDRSS_PHY_404_DATA 0x00000000
> +#define DDRSS_PHY_405_DATA 0x00000000
> +#define DDRSS_PHY_406_DATA 0x00000000
> +#define DDRSS_PHY_407_DATA 0x00000000
> +#define DDRSS_PHY_408_DATA 0x00000000
> +#define DDRSS_PHY_409_DATA 0x00000000
> +#define DDRSS_PHY_410_DATA 0x00000000
> +#define DDRSS_PHY_411_DATA 0x00000000
> +#define DDRSS_PHY_412_DATA 0x00000000
> +#define DDRSS_PHY_413_DATA 0x00000000
> +#define DDRSS_PHY_414_DATA 0x00000000
> +#define DDRSS_PHY_415_DATA 0x00000000
> +#define DDRSS_PHY_416_DATA 0x00000000
> +#define DDRSS_PHY_417_DATA 0x00000000
> +#define DDRSS_PHY_418_DATA 0x00000000
> +#define DDRSS_PHY_419_DATA 0x00000000
> +#define DDRSS_PHY_420_DATA 0x00000000
> +#define DDRSS_PHY_421_DATA 0x00000000
> +#define DDRSS_PHY_422_DATA 0x00000000
> +#define DDRSS_PHY_423_DATA 0x00000000
> +#define DDRSS_PHY_424_DATA 0x00000000
> +#define DDRSS_PHY_425_DATA 0x00000000
> +#define DDRSS_PHY_426_DATA 0x00000000
> +#define DDRSS_PHY_427_DATA 0x00000000
> +#define DDRSS_PHY_428_DATA 0x00000000
> +#define DDRSS_PHY_429_DATA 0x00000000
> +#define DDRSS_PHY_430_DATA 0x00000000
> +#define DDRSS_PHY_431_DATA 0x00000000
> +#define DDRSS_PHY_432_DATA 0x00000000
> +#define DDRSS_PHY_433_DATA 0x00000000
> +#define DDRSS_PHY_434_DATA 0x00000000
> +#define DDRSS_PHY_435_DATA 0x00000000
> +#define DDRSS_PHY_436_DATA 0x00000000
> +#define DDRSS_PHY_437_DATA 0x00000000
> +#define DDRSS_PHY_438_DATA 0x00000000
> +#define DDRSS_PHY_439_DATA 0x00000000
> +#define DDRSS_PHY_440_DATA 0x00000000
> +#define DDRSS_PHY_441_DATA 0x00000000
> +#define DDRSS_PHY_442_DATA 0x00000000
> +#define DDRSS_PHY_443_DATA 0x00000000
> +#define DDRSS_PHY_444_DATA 0x00000000
> +#define DDRSS_PHY_445_DATA 0x00000000
> +#define DDRSS_PHY_446_DATA 0x00000000
> +#define DDRSS_PHY_447_DATA 0x00000000
> +#define DDRSS_PHY_448_DATA 0x00000000
> +#define DDRSS_PHY_449_DATA 0x00000000
> +#define DDRSS_PHY_450_DATA 0x00000000
> +#define DDRSS_PHY_451_DATA 0x00000000
> +#define DDRSS_PHY_452_DATA 0x00000000
> +#define DDRSS_PHY_453_DATA 0x00000000
> +#define DDRSS_PHY_454_DATA 0x00000000
> +#define DDRSS_PHY_455_DATA 0x00000000
> +#define DDRSS_PHY_456_DATA 0x00000000
> +#define DDRSS_PHY_457_DATA 0x00000000
> +#define DDRSS_PHY_458_DATA 0x00000000
> +#define DDRSS_PHY_459_DATA 0x00000000
> +#define DDRSS_PHY_460_DATA 0x00000000
> +#define DDRSS_PHY_461_DATA 0x00000000
> +#define DDRSS_PHY_462_DATA 0x00000000
> +#define DDRSS_PHY_463_DATA 0x00000000
> +#define DDRSS_PHY_464_DATA 0x00000000
> +#define DDRSS_PHY_465_DATA 0x00000000
> +#define DDRSS_PHY_466_DATA 0x00000000
> +#define DDRSS_PHY_467_DATA 0x00000000
> +#define DDRSS_PHY_468_DATA 0x00000000
> +#define DDRSS_PHY_469_DATA 0x00000000
> +#define DDRSS_PHY_470_DATA 0x00000000
> +#define DDRSS_PHY_471_DATA 0x00000000
> +#define DDRSS_PHY_472_DATA 0x00000000
> +#define DDRSS_PHY_473_DATA 0x00000000
> +#define DDRSS_PHY_474_DATA 0x00000000
> +#define DDRSS_PHY_475_DATA 0x00000000
> +#define DDRSS_PHY_476_DATA 0x00000000
> +#define DDRSS_PHY_477_DATA 0x00000000
> +#define DDRSS_PHY_478_DATA 0x00000000
> +#define DDRSS_PHY_479_DATA 0x00000000
> +#define DDRSS_PHY_480_DATA 0x00000000
> +#define DDRSS_PHY_481_DATA 0x00000000
> +#define DDRSS_PHY_482_DATA 0x00000000
> +#define DDRSS_PHY_483_DATA 0x00000000
> +#define DDRSS_PHY_484_DATA 0x00000000
> +#define DDRSS_PHY_485_DATA 0x00000000
> +#define DDRSS_PHY_486_DATA 0x00000000
> +#define DDRSS_PHY_487_DATA 0x00000000
> +#define DDRSS_PHY_488_DATA 0x00000000
> +#define DDRSS_PHY_489_DATA 0x00000000
> +#define DDRSS_PHY_490_DATA 0x00000000
> +#define DDRSS_PHY_491_DATA 0x00000000
> +#define DDRSS_PHY_492_DATA 0x00000000
> +#define DDRSS_PHY_493_DATA 0x00000000
> +#define DDRSS_PHY_494_DATA 0x00000000
> +#define DDRSS_PHY_495_DATA 0x00000000
> +#define DDRSS_PHY_496_DATA 0x00000000
> +#define DDRSS_PHY_497_DATA 0x00000000
> +#define DDRSS_PHY_498_DATA 0x00000000
> +#define DDRSS_PHY_499_DATA 0x00000000
> +#define DDRSS_PHY_500_DATA 0x00000000
> +#define DDRSS_PHY_501_DATA 0x00000000
> +#define DDRSS_PHY_502_DATA 0x00000000
> +#define DDRSS_PHY_503_DATA 0x00000000
> +#define DDRSS_PHY_504_DATA 0x00000000
> +#define DDRSS_PHY_505_DATA 0x00000000
> +#define DDRSS_PHY_506_DATA 0x00000000
> +#define DDRSS_PHY_507_DATA 0x00000000
> +#define DDRSS_PHY_508_DATA 0x00000000
> +#define DDRSS_PHY_509_DATA 0x00000000
> +#define DDRSS_PHY_510_DATA 0x00000000
> +#define DDRSS_PHY_511_DATA 0x00000000
> +#define DDRSS_PHY_512_DATA 0x00000100
> +#define DDRSS_PHY_513_DATA 0x00000000
> +#define DDRSS_PHY_514_DATA 0x00000000
> +#define DDRSS_PHY_515_DATA 0x00000000
> +#define DDRSS_PHY_516_DATA 0x00000000
> +#define DDRSS_PHY_517_DATA 0x00000100
> +#define DDRSS_PHY_518_DATA 0x00000000
> +#define DDRSS_PHY_519_DATA 0x00000000
> +#define DDRSS_PHY_520_DATA 0x00000000
> +#define DDRSS_PHY_521_DATA 0x00000000
> +#define DDRSS_PHY_522_DATA 0x00000000
> +#define DDRSS_PHY_523_DATA 0x00000000
> +#define DDRSS_PHY_524_DATA 0x00000000
> +#define DDRSS_PHY_525_DATA 0x00DCBA98
> +#define DDRSS_PHY_526_DATA 0x00000000
> +#define DDRSS_PHY_527_DATA 0x00000000
> +#define DDRSS_PHY_528_DATA 0x00000000
> +#define DDRSS_PHY_529_DATA 0x00000000
> +#define DDRSS_PHY_530_DATA 0x00000000
> +#define DDRSS_PHY_531_DATA 0x00000000
> +#define DDRSS_PHY_532_DATA 0x00000000
> +#define DDRSS_PHY_533_DATA 0x00000000
> +#define DDRSS_PHY_534_DATA 0x00000000
> +#define DDRSS_PHY_535_DATA 0x00000000
> +#define DDRSS_PHY_536_DATA 0x00000000
> +#define DDRSS_PHY_537_DATA 0x00000000
> +#define DDRSS_PHY_538_DATA 0x00000000
> +#define DDRSS_PHY_539_DATA 0x00000000
> +#define DDRSS_PHY_540_DATA 0x0A418820
> +#define DDRSS_PHY_541_DATA 0x103F0000
> +#define DDRSS_PHY_542_DATA 0x000F0100
> +#define DDRSS_PHY_543_DATA 0x0000000F
> +#define DDRSS_PHY_544_DATA 0x020002CC
> +#define DDRSS_PHY_545_DATA 0x00030000
> +#define DDRSS_PHY_546_DATA 0x00000300
> +#define DDRSS_PHY_547_DATA 0x00000300
> +#define DDRSS_PHY_548_DATA 0x00000300
> +#define DDRSS_PHY_549_DATA 0x00000300
> +#define DDRSS_PHY_550_DATA 0x00000300
> +#define DDRSS_PHY_551_DATA 0x42080010
> +#define DDRSS_PHY_552_DATA 0x0000003E
> +#define DDRSS_PHY_553_DATA 0x00000000
> +#define DDRSS_PHY_554_DATA 0x00000000
> +#define DDRSS_PHY_555_DATA 0x00000000
> +#define DDRSS_PHY_556_DATA 0x00000000
> +#define DDRSS_PHY_557_DATA 0x00000000
> +#define DDRSS_PHY_558_DATA 0x00000000
> +#define DDRSS_PHY_559_DATA 0x00000000
> +#define DDRSS_PHY_560_DATA 0x00000000
> +#define DDRSS_PHY_561_DATA 0x00000000
> +#define DDRSS_PHY_562_DATA 0x00000000
> +#define DDRSS_PHY_563_DATA 0x00000000
> +#define DDRSS_PHY_564_DATA 0x00000000
> +#define DDRSS_PHY_565_DATA 0x00000000
> +#define DDRSS_PHY_566_DATA 0x00000000
> +#define DDRSS_PHY_567_DATA 0x00000000
> +#define DDRSS_PHY_568_DATA 0x00000000
> +#define DDRSS_PHY_569_DATA 0x00000000
> +#define DDRSS_PHY_570_DATA 0x00000000
> +#define DDRSS_PHY_571_DATA 0x00000000
> +#define DDRSS_PHY_572_DATA 0x00000000
> +#define DDRSS_PHY_573_DATA 0x00000000
> +#define DDRSS_PHY_574_DATA 0x00000000
> +#define DDRSS_PHY_575_DATA 0x00000000
> +#define DDRSS_PHY_576_DATA 0x00000000
> +#define DDRSS_PHY_577_DATA 0x00000000
> +#define DDRSS_PHY_578_DATA 0x00000000
> +#define DDRSS_PHY_579_DATA 0x00000000
> +#define DDRSS_PHY_580_DATA 0x00000000
> +#define DDRSS_PHY_581_DATA 0x00000000
> +#define DDRSS_PHY_582_DATA 0x00000000
> +#define DDRSS_PHY_583_DATA 0x00000000
> +#define DDRSS_PHY_584_DATA 0x00000000
> +#define DDRSS_PHY_585_DATA 0x00000000
> +#define DDRSS_PHY_586_DATA 0x00000000
> +#define DDRSS_PHY_587_DATA 0x00000000
> +#define DDRSS_PHY_588_DATA 0x00000000
> +#define DDRSS_PHY_589_DATA 0x00000000
> +#define DDRSS_PHY_590_DATA 0x00000000
> +#define DDRSS_PHY_591_DATA 0x00000000
> +#define DDRSS_PHY_592_DATA 0x00000000
> +#define DDRSS_PHY_593_DATA 0x00000000
> +#define DDRSS_PHY_594_DATA 0x00000000
> +#define DDRSS_PHY_595_DATA 0x00000000
> +#define DDRSS_PHY_596_DATA 0x00000000
> +#define DDRSS_PHY_597_DATA 0x00000000
> +#define DDRSS_PHY_598_DATA 0x00000000
> +#define DDRSS_PHY_599_DATA 0x00000000
> +#define DDRSS_PHY_600_DATA 0x00000000
> +#define DDRSS_PHY_601_DATA 0x00000000
> +#define DDRSS_PHY_602_DATA 0x00000000
> +#define DDRSS_PHY_603_DATA 0x00000000
> +#define DDRSS_PHY_604_DATA 0x00000000
> +#define DDRSS_PHY_605_DATA 0x00000000
> +#define DDRSS_PHY_606_DATA 0x00000000
> +#define DDRSS_PHY_607_DATA 0x00000000
> +#define DDRSS_PHY_608_DATA 0x00000000
> +#define DDRSS_PHY_609_DATA 0x00000000
> +#define DDRSS_PHY_610_DATA 0x00000000
> +#define DDRSS_PHY_611_DATA 0x00000000
> +#define DDRSS_PHY_612_DATA 0x00000000
> +#define DDRSS_PHY_613_DATA 0x00000000
> +#define DDRSS_PHY_614_DATA 0x00000000
> +#define DDRSS_PHY_615_DATA 0x00000000
> +#define DDRSS_PHY_616_DATA 0x00000000
> +#define DDRSS_PHY_617_DATA 0x00000000
> +#define DDRSS_PHY_618_DATA 0x00000000
> +#define DDRSS_PHY_619_DATA 0x00000000
> +#define DDRSS_PHY_620_DATA 0x00000000
> +#define DDRSS_PHY_621_DATA 0x00000000
> +#define DDRSS_PHY_622_DATA 0x00000000
> +#define DDRSS_PHY_623_DATA 0x00000000
> +#define DDRSS_PHY_624_DATA 0x00000000
> +#define DDRSS_PHY_625_DATA 0x00000000
> +#define DDRSS_PHY_626_DATA 0x00000000
> +#define DDRSS_PHY_627_DATA 0x00000000
> +#define DDRSS_PHY_628_DATA 0x00000000
> +#define DDRSS_PHY_629_DATA 0x00000000
> +#define DDRSS_PHY_630_DATA 0x00000000
> +#define DDRSS_PHY_631_DATA 0x00000000
> +#define DDRSS_PHY_632_DATA 0x00000000
> +#define DDRSS_PHY_633_DATA 0x00000000
> +#define DDRSS_PHY_634_DATA 0x00000000
> +#define DDRSS_PHY_635_DATA 0x00000000
> +#define DDRSS_PHY_636_DATA 0x00000000
> +#define DDRSS_PHY_637_DATA 0x00000000
> +#define DDRSS_PHY_638_DATA 0x00000000
> +#define DDRSS_PHY_639_DATA 0x00000000
> +#define DDRSS_PHY_640_DATA 0x00000000
> +#define DDRSS_PHY_641_DATA 0x00000000
> +#define DDRSS_PHY_642_DATA 0x00000000
> +#define DDRSS_PHY_643_DATA 0x00000000
> +#define DDRSS_PHY_644_DATA 0x00000000
> +#define DDRSS_PHY_645_DATA 0x00000000
> +#define DDRSS_PHY_646_DATA 0x00000000
> +#define DDRSS_PHY_647_DATA 0x00000000
> +#define DDRSS_PHY_648_DATA 0x00000000
> +#define DDRSS_PHY_649_DATA 0x00000000
> +#define DDRSS_PHY_650_DATA 0x00000000
> +#define DDRSS_PHY_651_DATA 0x00000000
> +#define DDRSS_PHY_652_DATA 0x00000000
> +#define DDRSS_PHY_653_DATA 0x00000000
> +#define DDRSS_PHY_654_DATA 0x00000000
> +#define DDRSS_PHY_655_DATA 0x00000000
> +#define DDRSS_PHY_656_DATA 0x00000000
> +#define DDRSS_PHY_657_DATA 0x00000000
> +#define DDRSS_PHY_658_DATA 0x00000000
> +#define DDRSS_PHY_659_DATA 0x00000000
> +#define DDRSS_PHY_660_DATA 0x00000000
> +#define DDRSS_PHY_661_DATA 0x00000000
> +#define DDRSS_PHY_662_DATA 0x00000000
> +#define DDRSS_PHY_663_DATA 0x00000000
> +#define DDRSS_PHY_664_DATA 0x00000000
> +#define DDRSS_PHY_665_DATA 0x00000000
> +#define DDRSS_PHY_666_DATA 0x00000000
> +#define DDRSS_PHY_667_DATA 0x00000000
> +#define DDRSS_PHY_668_DATA 0x00000000
> +#define DDRSS_PHY_669_DATA 0x00000000
> +#define DDRSS_PHY_670_DATA 0x00000000
> +#define DDRSS_PHY_671_DATA 0x00000000
> +#define DDRSS_PHY_672_DATA 0x00000000
> +#define DDRSS_PHY_673_DATA 0x00000000
> +#define DDRSS_PHY_674_DATA 0x00000000
> +#define DDRSS_PHY_675_DATA 0x00000000
> +#define DDRSS_PHY_676_DATA 0x00000000
> +#define DDRSS_PHY_677_DATA 0x00000000
> +#define DDRSS_PHY_678_DATA 0x00000000
> +#define DDRSS_PHY_679_DATA 0x00000000
> +#define DDRSS_PHY_680_DATA 0x00000000
> +#define DDRSS_PHY_681_DATA 0x00000000
> +#define DDRSS_PHY_682_DATA 0x00000000
> +#define DDRSS_PHY_683_DATA 0x00000000
> +#define DDRSS_PHY_684_DATA 0x00000000
> +#define DDRSS_PHY_685_DATA 0x00000000
> +#define DDRSS_PHY_686_DATA 0x00000000
> +#define DDRSS_PHY_687_DATA 0x00000000
> +#define DDRSS_PHY_688_DATA 0x00000000
> +#define DDRSS_PHY_689_DATA 0x00000000
> +#define DDRSS_PHY_690_DATA 0x00000000
> +#define DDRSS_PHY_691_DATA 0x00000000
> +#define DDRSS_PHY_692_DATA 0x00000000
> +#define DDRSS_PHY_693_DATA 0x00000000
> +#define DDRSS_PHY_694_DATA 0x00000000
> +#define DDRSS_PHY_695_DATA 0x00000000
> +#define DDRSS_PHY_696_DATA 0x00000000
> +#define DDRSS_PHY_697_DATA 0x00000000
> +#define DDRSS_PHY_698_DATA 0x00000000
> +#define DDRSS_PHY_699_DATA 0x00000000
> +#define DDRSS_PHY_700_DATA 0x00000000
> +#define DDRSS_PHY_701_DATA 0x00000000
> +#define DDRSS_PHY_702_DATA 0x00000000
> +#define DDRSS_PHY_703_DATA 0x00000000
> +#define DDRSS_PHY_704_DATA 0x00000000
> +#define DDRSS_PHY_705_DATA 0x00000000
> +#define DDRSS_PHY_706_DATA 0x00000000
> +#define DDRSS_PHY_707_DATA 0x00000000
> +#define DDRSS_PHY_708_DATA 0x00000000
> +#define DDRSS_PHY_709_DATA 0x00000000
> +#define DDRSS_PHY_710_DATA 0x00000000
> +#define DDRSS_PHY_711_DATA 0x00000000
> +#define DDRSS_PHY_712_DATA 0x00000000
> +#define DDRSS_PHY_713_DATA 0x00000000
> +#define DDRSS_PHY_714_DATA 0x00000000
> +#define DDRSS_PHY_715_DATA 0x00000000
> +#define DDRSS_PHY_716_DATA 0x00000000
> +#define DDRSS_PHY_717_DATA 0x00000000
> +#define DDRSS_PHY_718_DATA 0x00000000
> +#define DDRSS_PHY_719_DATA 0x00000000
> +#define DDRSS_PHY_720_DATA 0x00000000
> +#define DDRSS_PHY_721_DATA 0x00000000
> +#define DDRSS_PHY_722_DATA 0x00000000
> +#define DDRSS_PHY_723_DATA 0x00000000
> +#define DDRSS_PHY_724_DATA 0x00000000
> +#define DDRSS_PHY_725_DATA 0x00000000
> +#define DDRSS_PHY_726_DATA 0x00000000
> +#define DDRSS_PHY_727_DATA 0x00000000
> +#define DDRSS_PHY_728_DATA 0x00000000
> +#define DDRSS_PHY_729_DATA 0x00000000
> +#define DDRSS_PHY_730_DATA 0x00000000
> +#define DDRSS_PHY_731_DATA 0x00000000
> +#define DDRSS_PHY_732_DATA 0x00000000
> +#define DDRSS_PHY_733_DATA 0x00000000
> +#define DDRSS_PHY_734_DATA 0x00000000
> +#define DDRSS_PHY_735_DATA 0x00000000
> +#define DDRSS_PHY_736_DATA 0x00000000
> +#define DDRSS_PHY_737_DATA 0x00000000
> +#define DDRSS_PHY_738_DATA 0x00000000
> +#define DDRSS_PHY_739_DATA 0x00000000
> +#define DDRSS_PHY_740_DATA 0x00000000
> +#define DDRSS_PHY_741_DATA 0x00000000
> +#define DDRSS_PHY_742_DATA 0x00000000
> +#define DDRSS_PHY_743_DATA 0x00000000
> +#define DDRSS_PHY_744_DATA 0x00000000
> +#define DDRSS_PHY_745_DATA 0x00000000
> +#define DDRSS_PHY_746_DATA 0x00000000
> +#define DDRSS_PHY_747_DATA 0x00000000
> +#define DDRSS_PHY_748_DATA 0x00000000
> +#define DDRSS_PHY_749_DATA 0x00000000
> +#define DDRSS_PHY_750_DATA 0x00000000
> +#define DDRSS_PHY_751_DATA 0x00000000
> +#define DDRSS_PHY_752_DATA 0x00000000
> +#define DDRSS_PHY_753_DATA 0x00000000
> +#define DDRSS_PHY_754_DATA 0x00000000
> +#define DDRSS_PHY_755_DATA 0x00000000
> +#define DDRSS_PHY_756_DATA 0x00000000
> +#define DDRSS_PHY_757_DATA 0x00000000
> +#define DDRSS_PHY_758_DATA 0x00000000
> +#define DDRSS_PHY_759_DATA 0x00000000
> +#define DDRSS_PHY_760_DATA 0x00000000
> +#define DDRSS_PHY_761_DATA 0x00000000
> +#define DDRSS_PHY_762_DATA 0x00000000
> +#define DDRSS_PHY_763_DATA 0x00000000
> +#define DDRSS_PHY_764_DATA 0x00000000
> +#define DDRSS_PHY_765_DATA 0x00000000
> +#define DDRSS_PHY_766_DATA 0x00000000
> +#define DDRSS_PHY_767_DATA 0x00000000
> +#define DDRSS_PHY_768_DATA 0x00000100
> +#define DDRSS_PHY_769_DATA 0x00000000
> +#define DDRSS_PHY_770_DATA 0x00000000
> +#define DDRSS_PHY_771_DATA 0x00000000
> +#define DDRSS_PHY_772_DATA 0x00000000
> +#define DDRSS_PHY_773_DATA 0x00000100
> +#define DDRSS_PHY_774_DATA 0x00000000
> +#define DDRSS_PHY_775_DATA 0x00000000
> +#define DDRSS_PHY_776_DATA 0x00000000
> +#define DDRSS_PHY_777_DATA 0x00000000
> +#define DDRSS_PHY_778_DATA 0x00000000
> +#define DDRSS_PHY_779_DATA 0x00000000
> +#define DDRSS_PHY_780_DATA 0x00000000
> +#define DDRSS_PHY_781_DATA 0x00DCBA98
> +#define DDRSS_PHY_782_DATA 0x00000000
> +#define DDRSS_PHY_783_DATA 0x00000000
> +#define DDRSS_PHY_784_DATA 0x00000000
> +#define DDRSS_PHY_785_DATA 0x00000000
> +#define DDRSS_PHY_786_DATA 0x00000000
> +#define DDRSS_PHY_787_DATA 0x00000000
> +#define DDRSS_PHY_788_DATA 0x00000000
> +#define DDRSS_PHY_789_DATA 0x00000000
> +#define DDRSS_PHY_790_DATA 0x00000000
> +#define DDRSS_PHY_791_DATA 0x00000000
> +#define DDRSS_PHY_792_DATA 0x00000000
> +#define DDRSS_PHY_793_DATA 0x00000000
> +#define DDRSS_PHY_794_DATA 0x00000000
> +#define DDRSS_PHY_795_DATA 0x00000000
> +#define DDRSS_PHY_796_DATA 0x16A4A0E6
> +#define DDRSS_PHY_797_DATA 0x103F0000
> +#define DDRSS_PHY_798_DATA 0x000F0000
> +#define DDRSS_PHY_799_DATA 0x0000000F
> +#define DDRSS_PHY_800_DATA 0x020002CC
> +#define DDRSS_PHY_801_DATA 0x00030000
> +#define DDRSS_PHY_802_DATA 0x00000300
> +#define DDRSS_PHY_803_DATA 0x00000300
> +#define DDRSS_PHY_804_DATA 0x00000300
> +#define DDRSS_PHY_805_DATA 0x00000300
> +#define DDRSS_PHY_806_DATA 0x00000300
> +#define DDRSS_PHY_807_DATA 0x42080010
> +#define DDRSS_PHY_808_DATA 0x0000003E
> +#define DDRSS_PHY_809_DATA 0x00000000
> +#define DDRSS_PHY_810_DATA 0x00000000
> +#define DDRSS_PHY_811_DATA 0x00000000
> +#define DDRSS_PHY_812_DATA 0x00000000
> +#define DDRSS_PHY_813_DATA 0x00000000
> +#define DDRSS_PHY_814_DATA 0x00000000
> +#define DDRSS_PHY_815_DATA 0x00000000
> +#define DDRSS_PHY_816_DATA 0x00000000
> +#define DDRSS_PHY_817_DATA 0x00000000
> +#define DDRSS_PHY_818_DATA 0x00000000
> +#define DDRSS_PHY_819_DATA 0x00000000
> +#define DDRSS_PHY_820_DATA 0x00000000
> +#define DDRSS_PHY_821_DATA 0x00000000
> +#define DDRSS_PHY_822_DATA 0x00000000
> +#define DDRSS_PHY_823_DATA 0x00000000
> +#define DDRSS_PHY_824_DATA 0x00000000
> +#define DDRSS_PHY_825_DATA 0x00000000
> +#define DDRSS_PHY_826_DATA 0x00000000
> +#define DDRSS_PHY_827_DATA 0x00000000
> +#define DDRSS_PHY_828_DATA 0x00000000
> +#define DDRSS_PHY_829_DATA 0x00000000
> +#define DDRSS_PHY_830_DATA 0x00000000
> +#define DDRSS_PHY_831_DATA 0x00000000
> +#define DDRSS_PHY_832_DATA 0x00000000
> +#define DDRSS_PHY_833_DATA 0x00000000
> +#define DDRSS_PHY_834_DATA 0x00000000
> +#define DDRSS_PHY_835_DATA 0x00000000
> +#define DDRSS_PHY_836_DATA 0x00000000
> +#define DDRSS_PHY_837_DATA 0x00000000
> +#define DDRSS_PHY_838_DATA 0x00000000
> +#define DDRSS_PHY_839_DATA 0x00000000
> +#define DDRSS_PHY_840_DATA 0x00000000
> +#define DDRSS_PHY_841_DATA 0x00000000
> +#define DDRSS_PHY_842_DATA 0x00000000
> +#define DDRSS_PHY_843_DATA 0x00000000
> +#define DDRSS_PHY_844_DATA 0x00000000
> +#define DDRSS_PHY_845_DATA 0x00000000
> +#define DDRSS_PHY_846_DATA 0x00000000
> +#define DDRSS_PHY_847_DATA 0x00000000
> +#define DDRSS_PHY_848_DATA 0x00000000
> +#define DDRSS_PHY_849_DATA 0x00000000
> +#define DDRSS_PHY_850_DATA 0x00000000
> +#define DDRSS_PHY_851_DATA 0x00000000
> +#define DDRSS_PHY_852_DATA 0x00000000
> +#define DDRSS_PHY_853_DATA 0x00000000
> +#define DDRSS_PHY_854_DATA 0x00000000
> +#define DDRSS_PHY_855_DATA 0x00000000
> +#define DDRSS_PHY_856_DATA 0x00000000
> +#define DDRSS_PHY_857_DATA 0x00000000
> +#define DDRSS_PHY_858_DATA 0x00000000
> +#define DDRSS_PHY_859_DATA 0x00000000
> +#define DDRSS_PHY_860_DATA 0x00000000
> +#define DDRSS_PHY_861_DATA 0x00000000
> +#define DDRSS_PHY_862_DATA 0x00000000
> +#define DDRSS_PHY_863_DATA 0x00000000
> +#define DDRSS_PHY_864_DATA 0x00000000
> +#define DDRSS_PHY_865_DATA 0x00000000
> +#define DDRSS_PHY_866_DATA 0x00000000
> +#define DDRSS_PHY_867_DATA 0x00000000
> +#define DDRSS_PHY_868_DATA 0x00000000
> +#define DDRSS_PHY_869_DATA 0x00000000
> +#define DDRSS_PHY_870_DATA 0x00000000
> +#define DDRSS_PHY_871_DATA 0x00000000
> +#define DDRSS_PHY_872_DATA 0x00000000
> +#define DDRSS_PHY_873_DATA 0x00000000
> +#define DDRSS_PHY_874_DATA 0x00000000
> +#define DDRSS_PHY_875_DATA 0x00000000
> +#define DDRSS_PHY_876_DATA 0x00000000
> +#define DDRSS_PHY_877_DATA 0x00000000
> +#define DDRSS_PHY_878_DATA 0x00000000
> +#define DDRSS_PHY_879_DATA 0x00000000
> +#define DDRSS_PHY_880_DATA 0x00000000
> +#define DDRSS_PHY_881_DATA 0x00000000
> +#define DDRSS_PHY_882_DATA 0x00000000
> +#define DDRSS_PHY_883_DATA 0x00000000
> +#define DDRSS_PHY_884_DATA 0x00000000
> +#define DDRSS_PHY_885_DATA 0x00000000
> +#define DDRSS_PHY_886_DATA 0x00000000
> +#define DDRSS_PHY_887_DATA 0x00000000
> +#define DDRSS_PHY_888_DATA 0x00000000
> +#define DDRSS_PHY_889_DATA 0x00000000
> +#define DDRSS_PHY_890_DATA 0x00000000
> +#define DDRSS_PHY_891_DATA 0x00000000
> +#define DDRSS_PHY_892_DATA 0x00000000
> +#define DDRSS_PHY_893_DATA 0x00000000
> +#define DDRSS_PHY_894_DATA 0x00000000
> +#define DDRSS_PHY_895_DATA 0x00000000
> +#define DDRSS_PHY_896_DATA 0x00000000
> +#define DDRSS_PHY_897_DATA 0x00000000
> +#define DDRSS_PHY_898_DATA 0x00000000
> +#define DDRSS_PHY_899_DATA 0x00000000
> +#define DDRSS_PHY_900_DATA 0x00000000
> +#define DDRSS_PHY_901_DATA 0x00000000
> +#define DDRSS_PHY_902_DATA 0x00000000
> +#define DDRSS_PHY_903_DATA 0x00000000
> +#define DDRSS_PHY_904_DATA 0x00000000
> +#define DDRSS_PHY_905_DATA 0x00000000
> +#define DDRSS_PHY_906_DATA 0x00000000
> +#define DDRSS_PHY_907_DATA 0x00000000
> +#define DDRSS_PHY_908_DATA 0x00000000
> +#define DDRSS_PHY_909_DATA 0x00000000
> +#define DDRSS_PHY_910_DATA 0x00000000
> +#define DDRSS_PHY_911_DATA 0x00000000
> +#define DDRSS_PHY_912_DATA 0x00000000
> +#define DDRSS_PHY_913_DATA 0x00000000
> +#define DDRSS_PHY_914_DATA 0x00000000
> +#define DDRSS_PHY_915_DATA 0x00000000
> +#define DDRSS_PHY_916_DATA 0x00000000
> +#define DDRSS_PHY_917_DATA 0x00000000
> +#define DDRSS_PHY_918_DATA 0x00000000
> +#define DDRSS_PHY_919_DATA 0x00000000
> +#define DDRSS_PHY_920_DATA 0x00000000
> +#define DDRSS_PHY_921_DATA 0x00000000
> +#define DDRSS_PHY_922_DATA 0x00000000
> +#define DDRSS_PHY_923_DATA 0x00000000
> +#define DDRSS_PHY_924_DATA 0x00000000
> +#define DDRSS_PHY_925_DATA 0x00000000
> +#define DDRSS_PHY_926_DATA 0x00000000
> +#define DDRSS_PHY_927_DATA 0x00000000
> +#define DDRSS_PHY_928_DATA 0x00000000
> +#define DDRSS_PHY_929_DATA 0x00000000
> +#define DDRSS_PHY_930_DATA 0x00000000
> +#define DDRSS_PHY_931_DATA 0x00000000
> +#define DDRSS_PHY_932_DATA 0x00000000
> +#define DDRSS_PHY_933_DATA 0x00000000
> +#define DDRSS_PHY_934_DATA 0x00000000
> +#define DDRSS_PHY_935_DATA 0x00000000
> +#define DDRSS_PHY_936_DATA 0x00000000
> +#define DDRSS_PHY_937_DATA 0x00000000
> +#define DDRSS_PHY_938_DATA 0x00000000
> +#define DDRSS_PHY_939_DATA 0x00000000
> +#define DDRSS_PHY_940_DATA 0x00000000
> +#define DDRSS_PHY_941_DATA 0x00000000
> +#define DDRSS_PHY_942_DATA 0x00000000
> +#define DDRSS_PHY_943_DATA 0x00000000
> +#define DDRSS_PHY_944_DATA 0x00000000
> +#define DDRSS_PHY_945_DATA 0x00000000
> +#define DDRSS_PHY_946_DATA 0x00000000
> +#define DDRSS_PHY_947_DATA 0x00000000
> +#define DDRSS_PHY_948_DATA 0x00000000
> +#define DDRSS_PHY_949_DATA 0x00000000
> +#define DDRSS_PHY_950_DATA 0x00000000
> +#define DDRSS_PHY_951_DATA 0x00000000
> +#define DDRSS_PHY_952_DATA 0x00000000
> +#define DDRSS_PHY_953_DATA 0x00000000
> +#define DDRSS_PHY_954_DATA 0x00000000
> +#define DDRSS_PHY_955_DATA 0x00000000
> +#define DDRSS_PHY_956_DATA 0x00000000
> +#define DDRSS_PHY_957_DATA 0x00000000
> +#define DDRSS_PHY_958_DATA 0x00000000
> +#define DDRSS_PHY_959_DATA 0x00000000
> +#define DDRSS_PHY_960_DATA 0x00000000
> +#define DDRSS_PHY_961_DATA 0x00000000
> +#define DDRSS_PHY_962_DATA 0x00000000
> +#define DDRSS_PHY_963_DATA 0x00000000
> +#define DDRSS_PHY_964_DATA 0x00000000
> +#define DDRSS_PHY_965_DATA 0x00000000
> +#define DDRSS_PHY_966_DATA 0x00000000
> +#define DDRSS_PHY_967_DATA 0x00000000
> +#define DDRSS_PHY_968_DATA 0x00000000
> +#define DDRSS_PHY_969_DATA 0x00000000
> +#define DDRSS_PHY_970_DATA 0x00000000
> +#define DDRSS_PHY_971_DATA 0x00000000
> +#define DDRSS_PHY_972_DATA 0x00000000
> +#define DDRSS_PHY_973_DATA 0x00000000
> +#define DDRSS_PHY_974_DATA 0x00000000
> +#define DDRSS_PHY_975_DATA 0x00000000
> +#define DDRSS_PHY_976_DATA 0x00000000
> +#define DDRSS_PHY_977_DATA 0x00000000
> +#define DDRSS_PHY_978_DATA 0x00000000
> +#define DDRSS_PHY_979_DATA 0x00000000
> +#define DDRSS_PHY_980_DATA 0x00000000
> +#define DDRSS_PHY_981_DATA 0x00000000
> +#define DDRSS_PHY_982_DATA 0x00000000
> +#define DDRSS_PHY_983_DATA 0x00000000
> +#define DDRSS_PHY_984_DATA 0x00000000
> +#define DDRSS_PHY_985_DATA 0x00000000
> +#define DDRSS_PHY_986_DATA 0x00000000
> +#define DDRSS_PHY_987_DATA 0x00000000
> +#define DDRSS_PHY_988_DATA 0x00000000
> +#define DDRSS_PHY_989_DATA 0x00000000
> +#define DDRSS_PHY_990_DATA 0x00000000
> +#define DDRSS_PHY_991_DATA 0x00000000
> +#define DDRSS_PHY_992_DATA 0x00000000
> +#define DDRSS_PHY_993_DATA 0x00000000
> +#define DDRSS_PHY_994_DATA 0x00000000
> +#define DDRSS_PHY_995_DATA 0x00000000
> +#define DDRSS_PHY_996_DATA 0x00000000
> +#define DDRSS_PHY_997_DATA 0x00000000
> +#define DDRSS_PHY_998_DATA 0x00000000
> +#define DDRSS_PHY_999_DATA 0x00000000
> +#define DDRSS_PHY_1000_DATA 0x00000000
> +#define DDRSS_PHY_1001_DATA 0x00000000
> +#define DDRSS_PHY_1002_DATA 0x00000000
> +#define DDRSS_PHY_1003_DATA 0x00000000
> +#define DDRSS_PHY_1004_DATA 0x00000000
> +#define DDRSS_PHY_1005_DATA 0x00000000
> +#define DDRSS_PHY_1006_DATA 0x00000000
> +#define DDRSS_PHY_1007_DATA 0x00000000
> +#define DDRSS_PHY_1008_DATA 0x00000000
> +#define DDRSS_PHY_1009_DATA 0x00000000
> +#define DDRSS_PHY_1010_DATA 0x00000000
> +#define DDRSS_PHY_1011_DATA 0x00000000
> +#define DDRSS_PHY_1012_DATA 0x00000000
> +#define DDRSS_PHY_1013_DATA 0x00000000
> +#define DDRSS_PHY_1014_DATA 0x00000000
> +#define DDRSS_PHY_1015_DATA 0x00000000
> +#define DDRSS_PHY_1016_DATA 0x00000000
> +#define DDRSS_PHY_1017_DATA 0x00000000
> +#define DDRSS_PHY_1018_DATA 0x00000000
> +#define DDRSS_PHY_1019_DATA 0x00000000
> +#define DDRSS_PHY_1020_DATA 0x00000000
> +#define DDRSS_PHY_1021_DATA 0x00000000
> +#define DDRSS_PHY_1022_DATA 0x00000000
> +#define DDRSS_PHY_1023_DATA 0x00000000
> +#define DDRSS_PHY_1024_DATA 0x00000100
> +#define DDRSS_PHY_1025_DATA 0x00000000
> +#define DDRSS_PHY_1026_DATA 0x00000000
> +#define DDRSS_PHY_1027_DATA 0x00000000
> +#define DDRSS_PHY_1028_DATA 0x00000000
> +#define DDRSS_PHY_1029_DATA 0x00000100
> +#define DDRSS_PHY_1030_DATA 0x00000000
> +#define DDRSS_PHY_1031_DATA 0x00000000
> +#define DDRSS_PHY_1032_DATA 0x00000000
> +#define DDRSS_PHY_1033_DATA 0x00000000
> +#define DDRSS_PHY_1034_DATA 0x00000000
> +#define DDRSS_PHY_1035_DATA 0x00000000
> +#define DDRSS_PHY_1036_DATA 0x00000000
> +#define DDRSS_PHY_1037_DATA 0x00DCBA98
> +#define DDRSS_PHY_1038_DATA 0x00000000
> +#define DDRSS_PHY_1039_DATA 0x00000000
> +#define DDRSS_PHY_1040_DATA 0x00000000
> +#define DDRSS_PHY_1041_DATA 0x00000000
> +#define DDRSS_PHY_1042_DATA 0x00000000
> +#define DDRSS_PHY_1043_DATA 0x00000000
> +#define DDRSS_PHY_1044_DATA 0x00000000
> +#define DDRSS_PHY_1045_DATA 0x00000000
> +#define DDRSS_PHY_1046_DATA 0x00000000
> +#define DDRSS_PHY_1047_DATA 0x00000000
> +#define DDRSS_PHY_1048_DATA 0x00000000
> +#define DDRSS_PHY_1049_DATA 0x00000000
> +#define DDRSS_PHY_1050_DATA 0x00000000
> +#define DDRSS_PHY_1051_DATA 0x00000000
> +#define DDRSS_PHY_1052_DATA 0x2307B9AC
> +#define DDRSS_PHY_1053_DATA 0x10030000
> +#define DDRSS_PHY_1054_DATA 0x000F0000
> +#define DDRSS_PHY_1055_DATA 0x0000000F
> +#define DDRSS_PHY_1056_DATA 0x020002CC
> +#define DDRSS_PHY_1057_DATA 0x00030000
> +#define DDRSS_PHY_1058_DATA 0x00000300
> +#define DDRSS_PHY_1059_DATA 0x00000300
> +#define DDRSS_PHY_1060_DATA 0x00000300
> +#define DDRSS_PHY_1061_DATA 0x00000300
> +#define DDRSS_PHY_1062_DATA 0x00000300
> +#define DDRSS_PHY_1063_DATA 0x42080010
> +#define DDRSS_PHY_1064_DATA 0x0000003E
> +#define DDRSS_PHY_1065_DATA 0x00000000
> +#define DDRSS_PHY_1066_DATA 0x00000000
> +#define DDRSS_PHY_1067_DATA 0x00000000
> +#define DDRSS_PHY_1068_DATA 0x00000000
> +#define DDRSS_PHY_1069_DATA 0x00000000
> +#define DDRSS_PHY_1070_DATA 0x00000000
> +#define DDRSS_PHY_1071_DATA 0x00000000
> +#define DDRSS_PHY_1072_DATA 0x00000000
> +#define DDRSS_PHY_1073_DATA 0x00000000
> +#define DDRSS_PHY_1074_DATA 0x00000000
> +#define DDRSS_PHY_1075_DATA 0x00000000
> +#define DDRSS_PHY_1076_DATA 0x00000000
> +#define DDRSS_PHY_1077_DATA 0x00000000
> +#define DDRSS_PHY_1078_DATA 0x00000000
> +#define DDRSS_PHY_1079_DATA 0x00000000
> +#define DDRSS_PHY_1080_DATA 0x00000000
> +#define DDRSS_PHY_1081_DATA 0x00000000
> +#define DDRSS_PHY_1082_DATA 0x00000000
> +#define DDRSS_PHY_1083_DATA 0x00000000
> +#define DDRSS_PHY_1084_DATA 0x00000000
> +#define DDRSS_PHY_1085_DATA 0x00000000
> +#define DDRSS_PHY_1086_DATA 0x00000000
> +#define DDRSS_PHY_1087_DATA 0x00000000
> +#define DDRSS_PHY_1088_DATA 0x00000000
> +#define DDRSS_PHY_1089_DATA 0x00000000
> +#define DDRSS_PHY_1090_DATA 0x00000000
> +#define DDRSS_PHY_1091_DATA 0x00000000
> +#define DDRSS_PHY_1092_DATA 0x00000000
> +#define DDRSS_PHY_1093_DATA 0x00000000
> +#define DDRSS_PHY_1094_DATA 0x00000000
> +#define DDRSS_PHY_1095_DATA 0x00000000
> +#define DDRSS_PHY_1096_DATA 0x00000000
> +#define DDRSS_PHY_1097_DATA 0x00000000
> +#define DDRSS_PHY_1098_DATA 0x00000000
> +#define DDRSS_PHY_1099_DATA 0x00000000
> +#define DDRSS_PHY_1100_DATA 0x00000000
> +#define DDRSS_PHY_1101_DATA 0x00000000
> +#define DDRSS_PHY_1102_DATA 0x00000000
> +#define DDRSS_PHY_1103_DATA 0x00000000
> +#define DDRSS_PHY_1104_DATA 0x00000000
> +#define DDRSS_PHY_1105_DATA 0x00000000
> +#define DDRSS_PHY_1106_DATA 0x00000000
> +#define DDRSS_PHY_1107_DATA 0x00000000
> +#define DDRSS_PHY_1108_DATA 0x00000000
> +#define DDRSS_PHY_1109_DATA 0x00000000
> +#define DDRSS_PHY_1110_DATA 0x00000000
> +#define DDRSS_PHY_1111_DATA 0x00000000
> +#define DDRSS_PHY_1112_DATA 0x00000000
> +#define DDRSS_PHY_1113_DATA 0x00000000
> +#define DDRSS_PHY_1114_DATA 0x00000000
> +#define DDRSS_PHY_1115_DATA 0x00000000
> +#define DDRSS_PHY_1116_DATA 0x00000000
> +#define DDRSS_PHY_1117_DATA 0x00000000
> +#define DDRSS_PHY_1118_DATA 0x00000000
> +#define DDRSS_PHY_1119_DATA 0x00000000
> +#define DDRSS_PHY_1120_DATA 0x00000000
> +#define DDRSS_PHY_1121_DATA 0x00000000
> +#define DDRSS_PHY_1122_DATA 0x00000000
> +#define DDRSS_PHY_1123_DATA 0x00000000
> +#define DDRSS_PHY_1124_DATA 0x00000000
> +#define DDRSS_PHY_1125_DATA 0x00000000
> +#define DDRSS_PHY_1126_DATA 0x00000000
> +#define DDRSS_PHY_1127_DATA 0x00000000
> +#define DDRSS_PHY_1128_DATA 0x00000000
> +#define DDRSS_PHY_1129_DATA 0x00000000
> +#define DDRSS_PHY_1130_DATA 0x00000000
> +#define DDRSS_PHY_1131_DATA 0x00000000
> +#define DDRSS_PHY_1132_DATA 0x00000000
> +#define DDRSS_PHY_1133_DATA 0x00000000
> +#define DDRSS_PHY_1134_DATA 0x00000000
> +#define DDRSS_PHY_1135_DATA 0x00000000
> +#define DDRSS_PHY_1136_DATA 0x00000000
> +#define DDRSS_PHY_1137_DATA 0x00000000
> +#define DDRSS_PHY_1138_DATA 0x00000000
> +#define DDRSS_PHY_1139_DATA 0x00000000
> +#define DDRSS_PHY_1140_DATA 0x00000000
> +#define DDRSS_PHY_1141_DATA 0x00000000
> +#define DDRSS_PHY_1142_DATA 0x00000000
> +#define DDRSS_PHY_1143_DATA 0x00000000
> +#define DDRSS_PHY_1144_DATA 0x00000000
> +#define DDRSS_PHY_1145_DATA 0x00000000
> +#define DDRSS_PHY_1146_DATA 0x00000000
> +#define DDRSS_PHY_1147_DATA 0x00000000
> +#define DDRSS_PHY_1148_DATA 0x00000000
> +#define DDRSS_PHY_1149_DATA 0x00000000
> +#define DDRSS_PHY_1150_DATA 0x00000000
> +#define DDRSS_PHY_1151_DATA 0x00000000
> +#define DDRSS_PHY_1152_DATA 0x00000000
> +#define DDRSS_PHY_1153_DATA 0x00000000
> +#define DDRSS_PHY_1154_DATA 0x00000000
> +#define DDRSS_PHY_1155_DATA 0x00000000
> +#define DDRSS_PHY_1156_DATA 0x00000000
> +#define DDRSS_PHY_1157_DATA 0x00000000
> +#define DDRSS_PHY_1158_DATA 0x00000000
> +#define DDRSS_PHY_1159_DATA 0x00000000
> +#define DDRSS_PHY_1160_DATA 0x00000000
> +#define DDRSS_PHY_1161_DATA 0x00000000
> +#define DDRSS_PHY_1162_DATA 0x00000000
> +#define DDRSS_PHY_1163_DATA 0x00000000
> +#define DDRSS_PHY_1164_DATA 0x00000000
> +#define DDRSS_PHY_1165_DATA 0x00000000
> +#define DDRSS_PHY_1166_DATA 0x00000000
> +#define DDRSS_PHY_1167_DATA 0x00000000
> +#define DDRSS_PHY_1168_DATA 0x00000000
> +#define DDRSS_PHY_1169_DATA 0x00000000
> +#define DDRSS_PHY_1170_DATA 0x00000000
> +#define DDRSS_PHY_1171_DATA 0x00000000
> +#define DDRSS_PHY_1172_DATA 0x00000000
> +#define DDRSS_PHY_1173_DATA 0x00000000
> +#define DDRSS_PHY_1174_DATA 0x00000000
> +#define DDRSS_PHY_1175_DATA 0x00000000
> +#define DDRSS_PHY_1176_DATA 0x00000000
> +#define DDRSS_PHY_1177_DATA 0x00000000
> +#define DDRSS_PHY_1178_DATA 0x00000000
> +#define DDRSS_PHY_1179_DATA 0x00000000
> +#define DDRSS_PHY_1180_DATA 0x00000000
> +#define DDRSS_PHY_1181_DATA 0x00000000
> +#define DDRSS_PHY_1182_DATA 0x00000000
> +#define DDRSS_PHY_1183_DATA 0x00000000
> +#define DDRSS_PHY_1184_DATA 0x00000000
> +#define DDRSS_PHY_1185_DATA 0x00000000
> +#define DDRSS_PHY_1186_DATA 0x00000000
> +#define DDRSS_PHY_1187_DATA 0x00000000
> +#define DDRSS_PHY_1188_DATA 0x00000000
> +#define DDRSS_PHY_1189_DATA 0x00000000
> +#define DDRSS_PHY_1190_DATA 0x00000000
> +#define DDRSS_PHY_1191_DATA 0x00000000
> +#define DDRSS_PHY_1192_DATA 0x00000000
> +#define DDRSS_PHY_1193_DATA 0x00000000
> +#define DDRSS_PHY_1194_DATA 0x00000000
> +#define DDRSS_PHY_1195_DATA 0x00000000
> +#define DDRSS_PHY_1196_DATA 0x00000000
> +#define DDRSS_PHY_1197_DATA 0x00000000
> +#define DDRSS_PHY_1198_DATA 0x00000000
> +#define DDRSS_PHY_1199_DATA 0x00000000
> +#define DDRSS_PHY_1200_DATA 0x00000000
> +#define DDRSS_PHY_1201_DATA 0x00000000
> +#define DDRSS_PHY_1202_DATA 0x00000000
> +#define DDRSS_PHY_1203_DATA 0x00000000
> +#define DDRSS_PHY_1204_DATA 0x00000000
> +#define DDRSS_PHY_1205_DATA 0x00000000
> +#define DDRSS_PHY_1206_DATA 0x00000000
> +#define DDRSS_PHY_1207_DATA 0x00000000
> +#define DDRSS_PHY_1208_DATA 0x00000000
> +#define DDRSS_PHY_1209_DATA 0x00000000
> +#define DDRSS_PHY_1210_DATA 0x00000000
> +#define DDRSS_PHY_1211_DATA 0x00000000
> +#define DDRSS_PHY_1212_DATA 0x00000000
> +#define DDRSS_PHY_1213_DATA 0x00000000
> +#define DDRSS_PHY_1214_DATA 0x00000000
> +#define DDRSS_PHY_1215_DATA 0x00000000
> +#define DDRSS_PHY_1216_DATA 0x00000000
> +#define DDRSS_PHY_1217_DATA 0x00000000
> +#define DDRSS_PHY_1218_DATA 0x00000000
> +#define DDRSS_PHY_1219_DATA 0x00000000
> +#define DDRSS_PHY_1220_DATA 0x00000000
> +#define DDRSS_PHY_1221_DATA 0x00000000
> +#define DDRSS_PHY_1222_DATA 0x00000000
> +#define DDRSS_PHY_1223_DATA 0x00000000
> +#define DDRSS_PHY_1224_DATA 0x00000000
> +#define DDRSS_PHY_1225_DATA 0x00000000
> +#define DDRSS_PHY_1226_DATA 0x00000000
> +#define DDRSS_PHY_1227_DATA 0x00000000
> +#define DDRSS_PHY_1228_DATA 0x00000000
> +#define DDRSS_PHY_1229_DATA 0x00000000
> +#define DDRSS_PHY_1230_DATA 0x00000000
> +#define DDRSS_PHY_1231_DATA 0x00000000
> +#define DDRSS_PHY_1232_DATA 0x00000000
> +#define DDRSS_PHY_1233_DATA 0x00000000
> +#define DDRSS_PHY_1234_DATA 0x00000000
> +#define DDRSS_PHY_1235_DATA 0x00000000
> +#define DDRSS_PHY_1236_DATA 0x00000000
> +#define DDRSS_PHY_1237_DATA 0x00000000
> +#define DDRSS_PHY_1238_DATA 0x00000000
> +#define DDRSS_PHY_1239_DATA 0x00000000
> +#define DDRSS_PHY_1240_DATA 0x00000000
> +#define DDRSS_PHY_1241_DATA 0x00000000
> +#define DDRSS_PHY_1242_DATA 0x00000000
> +#define DDRSS_PHY_1243_DATA 0x00000000
> +#define DDRSS_PHY_1244_DATA 0x00000000
> +#define DDRSS_PHY_1245_DATA 0x00000000
> +#define DDRSS_PHY_1246_DATA 0x00000000
> +#define DDRSS_PHY_1247_DATA 0x00000000
> +#define DDRSS_PHY_1248_DATA 0x00000000
> +#define DDRSS_PHY_1249_DATA 0x00000000
> +#define DDRSS_PHY_1250_DATA 0x00000000
> +#define DDRSS_PHY_1251_DATA 0x00000000
> +#define DDRSS_PHY_1252_DATA 0x00000000
> +#define DDRSS_PHY_1253_DATA 0x00000000
> +#define DDRSS_PHY_1254_DATA 0x00000000
> +#define DDRSS_PHY_1255_DATA 0x00000000
> +#define DDRSS_PHY_1256_DATA 0x00000000
> +#define DDRSS_PHY_1257_DATA 0x00000000
> +#define DDRSS_PHY_1258_DATA 0x00000000
> +#define DDRSS_PHY_1259_DATA 0x00000000
> +#define DDRSS_PHY_1260_DATA 0x00000000
> +#define DDRSS_PHY_1261_DATA 0x00000000
> +#define DDRSS_PHY_1262_DATA 0x00000000
> +#define DDRSS_PHY_1263_DATA 0x00000000
> +#define DDRSS_PHY_1264_DATA 0x00000000
> +#define DDRSS_PHY_1265_DATA 0x00000000
> +#define DDRSS_PHY_1266_DATA 0x00000000
> +#define DDRSS_PHY_1267_DATA 0x00000000
> +#define DDRSS_PHY_1268_DATA 0x00000000
> +#define DDRSS_PHY_1269_DATA 0x00000000
> +#define DDRSS_PHY_1270_DATA 0x00000000
> +#define DDRSS_PHY_1271_DATA 0x00000000
> +#define DDRSS_PHY_1272_DATA 0x00000000
> +#define DDRSS_PHY_1273_DATA 0x00000000
> +#define DDRSS_PHY_1274_DATA 0x00000000
> +#define DDRSS_PHY_1275_DATA 0x00000000
> +#define DDRSS_PHY_1276_DATA 0x00000000
> +#define DDRSS_PHY_1277_DATA 0x00000000
> +#define DDRSS_PHY_1278_DATA 0x00000000
> +#define DDRSS_PHY_1279_DATA 0x00000000
> +#define DDRSS_PHY_1280_DATA 0x00000000
> +#define DDRSS_PHY_1281_DATA 0x00000100
> +#define DDRSS_PHY_1282_DATA 0x00000000
> +#define DDRSS_PHY_1283_DATA 0x00000000
> +#define DDRSS_PHY_1284_DATA 0x00000000
> +#define DDRSS_PHY_1285_DATA 0x00000000
> +#define DDRSS_PHY_1286_DATA 0x00050000
> +#define DDRSS_PHY_1287_DATA 0x04000100
> +#define DDRSS_PHY_1288_DATA 0x00000055
> +#define DDRSS_PHY_1289_DATA 0x00000000
> +#define DDRSS_PHY_1290_DATA 0x00000000
> +#define DDRSS_PHY_1291_DATA 0x00000000
> +#define DDRSS_PHY_1292_DATA 0x00000000
> +#define DDRSS_PHY_1293_DATA 0x01002000
> +#define DDRSS_PHY_1294_DATA 0x00004001
> +#define DDRSS_PHY_1295_DATA 0x00020028
> +#define DDRSS_PHY_1296_DATA 0x00010100
> +#define DDRSS_PHY_1297_DATA 0x00000001
> +#define DDRSS_PHY_1298_DATA 0x00000000
> +#define DDRSS_PHY_1299_DATA 0x0F0F0E06
> +#define DDRSS_PHY_1300_DATA 0x00010101
> +#define DDRSS_PHY_1301_DATA 0x010F0004
> +#define DDRSS_PHY_1302_DATA 0x00000000
> +#define DDRSS_PHY_1303_DATA 0x00000000
> +#define DDRSS_PHY_1304_DATA 0x00000064
> +#define DDRSS_PHY_1305_DATA 0x00000000
> +#define DDRSS_PHY_1306_DATA 0x00000000
> +#define DDRSS_PHY_1307_DATA 0x01020103
> +#define DDRSS_PHY_1308_DATA 0x0F020102
> +#define DDRSS_PHY_1309_DATA 0x03030303
> +#define DDRSS_PHY_1310_DATA 0x03030303
> +#define DDRSS_PHY_1311_DATA 0x00040000
> +#define DDRSS_PHY_1312_DATA 0x00004201
> +#define DDRSS_PHY_1313_DATA 0x00000000
> +#define DDRSS_PHY_1314_DATA 0x00000000
> +#define DDRSS_PHY_1315_DATA 0x00000000
> +#define DDRSS_PHY_1316_DATA 0x00000000
> +#define DDRSS_PHY_1317_DATA 0x00000000
> +#define DDRSS_PHY_1318_DATA 0x00000000
> +#define DDRSS_PHY_1319_DATA 0x07070001
> +#define DDRSS_PHY_1320_DATA 0x00005400
> +#define DDRSS_PHY_1321_DATA 0x000040A2
> +#define DDRSS_PHY_1322_DATA 0x00024410
> +#define DDRSS_PHY_1323_DATA 0x00004410
> +#define DDRSS_PHY_1324_DATA 0x00004410
> +#define DDRSS_PHY_1325_DATA 0x00004410
> +#define DDRSS_PHY_1326_DATA 0x00004410
> +#define DDRSS_PHY_1327_DATA 0x00004410
> +#define DDRSS_PHY_1328_DATA 0x00004410
> +#define DDRSS_PHY_1329_DATA 0x00004410
> +#define DDRSS_PHY_1330_DATA 0x00004410
> +#define DDRSS_PHY_1331_DATA 0x00004410
> +#define DDRSS_PHY_1332_DATA 0x00000000
> +#define DDRSS_PHY_1333_DATA 0x00000046
> +#define DDRSS_PHY_1334_DATA 0x00000400
> +#define DDRSS_PHY_1335_DATA 0x00000008
> +#define DDRSS_PHY_1336_DATA 0x00000000
> +#define DDRSS_PHY_1337_DATA 0x00000000
> +#define DDRSS_PHY_1338_DATA 0x00000000
> +#define DDRSS_PHY_1339_DATA 0x00000000
> +#define DDRSS_PHY_1340_DATA 0x00000000
> +#define DDRSS_PHY_1341_DATA 0x03000000
> +#define DDRSS_PHY_1342_DATA 0x00000000
> +#define DDRSS_PHY_1343_DATA 0x00000000
> +#define DDRSS_PHY_1344_DATA 0x00000000
> +#define DDRSS_PHY_1345_DATA 0x04102006
> +#define DDRSS_PHY_1346_DATA 0x00041020
> +#define DDRSS_PHY_1347_DATA 0x01C98C98
> +#define DDRSS_PHY_1348_DATA 0x3F400000
> +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
> +#define DDRSS_PHY_1350_DATA 0x0000001F
> +#define DDRSS_PHY_1351_DATA 0x00000000
> +#define DDRSS_PHY_1352_DATA 0x00000000
> +#define DDRSS_PHY_1353_DATA 0x00000000
> +#define DDRSS_PHY_1354_DATA 0x00000001
> +#define DDRSS_PHY_1355_DATA 0x00000000
> +#define DDRSS_PHY_1356_DATA 0x00000000
> +#define DDRSS_PHY_1357_DATA 0x00000000
> +#define DDRSS_PHY_1358_DATA 0x00000000
> +#define DDRSS_PHY_1359_DATA 0x76543210
> +#define DDRSS_PHY_1360_DATA 0x00000098
> +#define DDRSS_PHY_1361_DATA 0x00000000
> +#define DDRSS_PHY_1362_DATA 0x00000000
> +#define DDRSS_PHY_1363_DATA 0x00000000
> +#define DDRSS_PHY_1364_DATA 0x00040700
> +#define DDRSS_PHY_1365_DATA 0x00000000
> +#define DDRSS_PHY_1366_DATA 0x00000000
> +#define DDRSS_PHY_1367_DATA 0x00000000
> +#define DDRSS_PHY_1368_DATA 0x00000002
> +#define DDRSS_PHY_1369_DATA 0x00000100
> +#define DDRSS_PHY_1370_DATA 0x00000000
> +#define DDRSS_PHY_1371_DATA 0x00000FC3
> +#define DDRSS_PHY_1372_DATA 0x00020002
> +#define DDRSS_PHY_1373_DATA 0x00000000
> +#define DDRSS_PHY_1374_DATA 0x00001142
> +#define DDRSS_PHY_1375_DATA 0x03020400
> +#define DDRSS_PHY_1376_DATA 0x00000080
> +#define DDRSS_PHY_1377_DATA 0x03900390
> +#define DDRSS_PHY_1378_DATA 0x03900390
> +#define DDRSS_PHY_1379_DATA 0x03900390
> +#define DDRSS_PHY_1380_DATA 0x03900390
> +#define DDRSS_PHY_1381_DATA 0x03900390
> +#define DDRSS_PHY_1382_DATA 0x03900390
> +#define DDRSS_PHY_1383_DATA 0x00000300
> +#define DDRSS_PHY_1384_DATA 0x00000300
> +#define DDRSS_PHY_1385_DATA 0x00000300
> +#define DDRSS_PHY_1386_DATA 0x00000300
> +#define DDRSS_PHY_1387_DATA 0x31823FC7
> +#define DDRSS_PHY_1388_DATA 0x00000000
> +#define DDRSS_PHY_1389_DATA 0x0C000D3F
> +#define DDRSS_PHY_1390_DATA 0x30000D3F
> +#define DDRSS_PHY_1391_DATA 0x300D3F11
> +#define DDRSS_PHY_1392_DATA 0x01990000
> +#define DDRSS_PHY_1393_DATA 0x000D3FCC
> +#define DDRSS_PHY_1394_DATA 0x00000C11
> +#define DDRSS_PHY_1395_DATA 0x300D3F11
> +#define DDRSS_PHY_1396_DATA 0x01990000
> +#define DDRSS_PHY_1397_DATA 0x300C3F11
> +#define DDRSS_PHY_1398_DATA 0x01990000
> +#define DDRSS_PHY_1399_DATA 0x300C3F11
> +#define DDRSS_PHY_1400_DATA 0x01990000
> +#define DDRSS_PHY_1401_DATA 0x300D3F11
> +#define DDRSS_PHY_1402_DATA 0x01990000
> +#define DDRSS_PHY_1403_DATA 0x300D3F11
> +#define DDRSS_PHY_1404_DATA 0x01990000
> +#define DDRSS_PHY_1405_DATA 0x20040004
> diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
> new file mode 100644
> index 000000000000..879a8dd68f3f
> --- /dev/null
> +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * https://beagleboard.org/play
> + *
> + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
> + */
> +
> +#include "k3-am625-sk-binman.dtsi"
> +
> +/ {
> + chosen {
> + tick-timer = &main_timer0;
> + };
> +
> + memory at 80000000 {
> + bootph-pre-ram;
> + };
> +
> + /* Keep the LEDs on by default to indicate life */
> + leds {
> + bootph-pre-ram;
> + led-0 {
> + default-state = "on";
> + bootph-pre-ram;
> + };
> +
> + led-1 {
> + default-state = "on";
> + bootph-pre-ram;
> + };
> +
> + led-2 {
> + default-state = "on";
> + bootph-pre-ram;
> + };
> +
> + led-3 {
> + default-state = "on";
> + bootph-pre-ram;
> + };
> +
> + led-4 {
> + default-state = "on";
> + bootph-pre-ram;
> + };
> + };
> +};
> +
> +&cbass_main {
> + bootph-pre-ram;
> +};
> +
> +&main_timer0 {
> + clock-frequency = <25000000>;
> + bootph-pre-ram;
> +};
> +
> +&dmss {
> + bootph-pre-ram;
> +};
> +
> +&secure_proxy_main {
> + bootph-pre-ram;
> +};
> +
> +&dmsc {
> + bootph-pre-ram;
> +};
> +
> +&k3_pds {
> + bootph-pre-ram;
> +};
> +
> +&k3_clks {
> + bootph-pre-ram;
> +};
> +
> +&k3_reset {
> + bootph-pre-ram;
> +};
> +
> +&dmsc {
> + bootph-pre-ram;
> + k3_sysreset: sysreset-controller {
> + compatible = "ti,sci-sysreset";
> + bootph-pre-ram;
> + };
> +};
> +
> +&wkup_conf {
> + bootph-pre-ram;
> +};
> +
> +&chipid {
> + bootph-pre-ram;
> +};
> +
> +&main_pmx0 {
> + bootph-pre-ram;
> +};
> +
> +&main_uart0 {
> + bootph-pre-ram;
> +};
> +
> +&console_pins_default {
> + bootph-pre-ram;
> +};
> +
> +&cbass_mcu {
> + bootph-pre-ram;
> +};
> +
> +&cbass_wakeup {
> + bootph-pre-ram;
> +};
> +
> +&mcu_pmx0 {
> + bootph-pre-ram;
> +};
> +
> +
> +&main_i2c0 {
> + bootph-pre-ram;
> +};
> +
> +&local_i2c_pins_default {
> + bootph-pre-ram;
> +};
> +
> +&gpio0_pins_default {
> + bootph-pre-ram;
> +};
> +
> +&main_gpio0 {
> + bootph-pre-ram;
> +};
> +
> +&main_gpio1 {
> + bootph-pre-ram;
> +};
> +
> +&sdhci0 {
> + /* EMMC */
> + bootph-pre-ram;
> +};
> +
> +&emmc_pins_default {
> + bootph-pre-ram;
> +};
> +
> +&sd_pins_default {
> + bootph-pre-ram;
> + /* Force to use SDCD card detect pin */
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
> + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
> + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
> + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
> + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
> + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
> + AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD.MMC1_SDCD */
> + >;
> +};
> +
> +&tps65219 {
> + bootph-pre-ram;
> +};
> +
> +&sdhci1 {
> + bootph-pre-ram;
> +};
> +
> +#ifdef CONFIG_TARGET_AM625_A53_EVM
> +
> +#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
> +#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
> +
> +&spl_am625_sk_dtb {
> + filename = SPL_AM625_BEAGLEPLAY_DTB;
> +};
> +
> +&am625_sk_dtb {
> + filename = AM625_BEAGLEPLAY_DTB;
> +};
> +
> +&spl_am625_sk_dtb_unsigned {
> + filename = SPL_AM625_BEAGLEPLAY_DTB;
> +};
> +
> +&am625_sk_dtb_unsigned {
> + filename = AM625_BEAGLEPLAY_DTB;
> +};
> +
> +#endif
> diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
> new file mode 100644
> index 000000000000..589bf998bc52
> --- /dev/null
> +++ b/arch/arm/dts/k3-am625-beagleplay.dts
> @@ -0,0 +1,758 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * https://beagleplay.org/
> + *
> + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "k3-am625.dtsi"
> +
> +/ {
> + compatible = "beagle,am625-beagleplay", "ti,am625";
> + model = "BeagleBoard.org BeaglePlay";
> +
> + aliases {
> + ethernet0 = &cpsw_port1;
> + ethernet1 = &cpsw_port2;
> + gpio0 = &main_gpio0;
> + gpio1 = &main_gpio1;
> + gpio2 = &mcu_gpio0;
> + i2c0 = &main_i2c0;
> + i2c1 = &main_i2c1;
> + i2c2 = &main_i2c2;
> + i2c3 = &main_i2c3;
> + i2c4 = &wkup_i2c0;
> + i2c5 = &mcu_i2c0;
> + mdio-gpio0 = &mdio0;
> + mmc0 = &sdhci0;
> + mmc1 = &sdhci1;
> + mmc2 = &sdhci2;
> + rtc0 = &rtc;
> + serial0 = &main_uart5;
> + serial1 = &main_uart6;
> + serial2 = &main_uart0;
> + usb0 = &usb0;
> + usb1 = &usb1;
> + };
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + /* 2G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ramoops: ramoops at 9ca00000 {
> + compatible = "ramoops";
> + reg = <0x00 0x9c700000 0x00 0x00100000>;
> + record-size = <0x8000>;
> + console-size = <0x8000>;
> + ftrace-size = <0x00>;
> + pmsg-size = <0x8000>;
> + };
> +
> + secure_tfa_ddr: tfa at 9e780000 {
> + reg = <0x00 0x9e780000 0x00 0x80000>;
> + no-map;
> + };
> +
> + secure_ddr: optee at 9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory at 9db00000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9db00000 0x00 0xc00000>;
> + no-map;
> + };
> + };
> +
> + vsys_5v0: regulator-1 {
> + compatible = "regulator-fixed";
> + regulator-name = "vsys_5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_3v3: regulator-2 {
> + /* output of TLV62595DMQR-U12 */
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vsys_5v0>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + wlan_en: regulator-3 {
> + /* OUTPUT of SN74AVC2T244DQMR */
> + compatible = "regulator-fixed";
> + regulator-name = "wlan_en";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <&vdd_3v3>;
> + gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_en_pins_default>;
> + };
> +
> + vdd_3v3_sd: regulator-4 {
> + /* output of TPS22918DBVR-U21 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&vdd_3v3_sd_pins_default>;
> +
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_3v3_sd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-always-on;
> + vin-supply = <&vdd_3v3>;
> + gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
> + };
> +
> + vdd_sd_dv: regulator-5 {
> + compatible = "regulator-gpio";
> + regulator-name = "sd_hs200_switch";
> + pinctrl-names = "default";
> + pinctrl-0 = <&vdd_sd_dv_pins_default>;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + vin-supply = <&ldo1_reg>;
> + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x0>,
> + <3300000 0x1>;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + function = LED_FUNCTION_HEARTBEAT;
> + default-state = "off";
> + };
> +
> + led-1 {
> + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "disk-activity";
> + function = LED_FUNCTION_DISK_ACTIVITY;
> + default-state = "keep";
> + };
> +
> + led-2 {
> + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
> + function = LED_FUNCTION_CPU;
> + };
> +
> + led-3 {
> + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
> + function = LED_FUNCTION_LAN;
> + };
> +
> + led-4 {
> + gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
> + function = LED_FUNCTION_WLAN;
> + };
> + };
> +
> + gpio_keys: gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usr_button_pins_default>;
> +
> + usr: button-usr {
> + label = "User Key";
> + linux,code = <BTN_0>;
> + gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>;
> + };
> +
> + };
> +
> + /* Workaround for errata i2329 - just use mdio bitbang */
> + mdio0: mdio {
> + compatible = "virtual,mdio-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mdio0_pins_default>;
> + gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
> + <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw3g_phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +
> + cpsw3g_phy1: ethernet-phy at 1 {
> + reg = <1>;
> + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <25>;
> + reset-deassert-us = <60000>; /* T2 */
> + };
> + };
> +};
> +
> +&main_pmx0 {
> + gpio0_pins_default: gpio0-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
> + AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
> + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */
> + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */
> + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */
> + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */
> + AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */
> + AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */
> + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */
> + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
> + AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
> + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */
> + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
> + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
> + >;
> + };
> +
> + vdd_sd_dv_pins_default: vdd-sd-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
> + >;
> + };
> +
> + usr_button_pins_default: usr-button-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
> + >;
> + };
> +
> + grove_pins_default: grove-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
> + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
> + >;
> + };
> +
> + local_i2c_pins_default: local-i2c-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
> + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
> + >;
> + };
> +
> + i2c2_1v8_pins_default: i2c2-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
> + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
> + >;
> + };
> +
> + mdio0_pins_default: mdio0-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
> + AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
> + >;
> + };
> +
> + rgmii1_pins_default: rgmii1-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
> + AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
> + AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
> + AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
> + AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
> + AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
> + AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
> + AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
> + AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
> + AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
> + AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
> + AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
> + >;
> + };
> +
> + emmc_pins_default: emmc-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
> + AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
> + AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
> + AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
> + AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
> + AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
> + AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
> + AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
> + AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
> + AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
> + >;
> + };
> +
> + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
> + >;
> + };
> +
> + sd_pins_default: sd-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
> + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
> + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
> + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
> + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
> + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
> + AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */
> + >;
> + };
> +
> + wifi_pins_default: wifi-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
> + AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
> + AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
> + AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
> + AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
> + AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
> + AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */
> + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
> + >;
> + };
> +
> + wifi_en_pins_default: wifi-en-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
> + >;
> + };
> +
> + wifi_wlirq_pins_default: wifi-wlirq-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
> + >;
> + };
> +
> + spe_pins_default: spe-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
> + AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
> + AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */
> + AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */
> + AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */
> + AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
> + AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
> + AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
> + AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
> + AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
> + AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
> + >;
> + };
> +
> + mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
> + AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
> + >;
> + };
> +
> + mikrobus_uart_pins_default: mikrobus-uart-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
> + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
> + >;
> + };
> +
> + mikrobus_spi_pins_default: mikrobus-spi-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
> + AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
> + AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
> + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
> + >;
> + };
> +
> + mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
> + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
> + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
> + >;
> + };
> +
> + console_pins_default: console-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
> + AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
> + >;
> + };
> +
> + wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
> + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
> + >;
> + };
> +
> + usb1_pins_default: usb1-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
> + >;
> + };
> +
> + pmic_irq_pins_default: pmic-irq-default-pins {
> + pinctrl-single,pins = <
> + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
> + >;
> + };
> +};
> +
> +&mcu_pmx0 {
> + i2c_qwiic_pins_default: i2c-qwiic-default-pins {
> + pinctrl-single,pins = <
> + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
> + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
> + >;
> + };
> +
> + gbe_pmx_obsclk: gbe-pmx-clk-default {
> + pinctrl-single,pins = <
> + AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
> + >;
> + };
> +
> + i2c_csi_pins_default: i2c-csi-default-pins {
> + pinctrl-single,pins = <
> + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
> + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
> + >;
> + };
> +
> + wifi_32k_clk: mcu-clk-out-default-pins {
> + pinctrl-single,pins = <
> + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
> + >;
> + };
> +};
> +
> +&a53_opp_table {
> + /* Requires VDD_CORE to be at 0.85V */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + };
> +};
> +
> +&wkup_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c_csi_pins_default>;
> + clock-frequency = <400000>;
> + /* Enable with overlay for camera sensor */
> +};
> +
> +&mcu_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c_qwiic_pins_default>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "peripheral";
> +};
> +
> +&usbss1 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb1_pins_default>;
> +};
> +
> +&cpsw3g {
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>,
> + <&gbe_pmx_obsclk>;
> + assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
> + assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
> +};
> +
> +&cpsw_port1 {
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&cpsw3g_phy0>;
> +};
> +
> +&cpsw_port2 {
> + phy-mode = "rmii";
> + phy-handle = <&cpsw3g_phy1>;
> +};
> +
> +&cpsw3g_mdio {
> + /* Workaround for errata i2329 - Use mdio bitbang */
> + status = "disabled";
> +};
> +
> +&main_gpio0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio0_pins_default>;
> + gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
> + "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
> + "EEPROM_WP", /* 10 */
> + "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
> + "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */
> + "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
> + "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
> + "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
> + "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */
> + "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */
> + "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */
> + "", "", "", "", "", "", /* 79-84 */
> + "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */
> + "", "", "", "", ""; /* 87-91 */
> +};
> +
> +&main_gpio1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mikrobus_gpio_pins_default>;
> + gpio-line-names = "", "", "", "", "", /* 0-4 */
> + "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */
> + "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */
> + "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */
> + "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */
> + "MIKROBUS_GPIO1_14", /* 14 */
> + "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */
> + "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */
> + "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */
> + "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */
> + "", "", "", "", "", "", "", "", "", "", /* 38-47 */
> + "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */
> +};
> +
> +&main_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&local_i2c_pins_default>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom at 50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> +
> + rtc: rtc at 68 {
> + compatible = "ti,bq32000";
> + reg = <0x68>;
> + interrupt-parent = <&main_gpio0>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + };
> +
> + tps65219: pmic at 30 {
> + compatible = "ti,tps65219";
> + reg = <0x30>;
> + buck1-supply = <&vsys_5v0>;
> + buck2-supply = <&vsys_5v0>;
> + buck3-supply = <&vsys_5v0>;
> + ldo1-supply = <&vdd_3v3>;
> + ldo2-supply = <&buck2_reg>;
> + ldo3-supply = <&vdd_3v3>;
> + ldo4-supply = <&vdd_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_irq_pins_default>;
> + interrupt-parent = <&gic500>;
> + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + system-power-controller;
> + ti,power-button;
> +
> + regulators {
> + buck1_reg: buck1 {
> + regulator-name = "VDD_CORE";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck2_reg: buck2 {
> + regulator-name = "VDD_1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck3_reg: buck3 {
> + regulator-name = "VDD_1V2";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: ldo1 {
> + /*
> + * Regulator is left as is unused, vdd_sd
> + * is controlled via GPIO with bypass config
> + * as per the NVM configuration
> + */
> + regulator-name = "VDD_SD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-allow-bypass;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: ldo2 {
> + regulator-name = "VDDA_0V85";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: ldo3 {
> + regulator-name = "VDDA_1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: ldo4 {
> + regulator-name = "VDD_2V5";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&main_i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&grove_pins_default>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&main_i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_1v8_pins_default>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&main_i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mikrobus_i2c_pins_default>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_spi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mikrobus_spi_pins_default>;
> + status = "okay";
> +};
> +
> +&sdhci0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_pins_default>;
> + ti,driver-strength-ohm = <50>;
> + disable-wp;
> + status = "okay";
> +};
> +
> +&sdhci1 {
> + /* SD/MMC */
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd_pins_default>;
> +
> + vmmc-supply = <&vdd_3v3_sd>;
> + vqmmc-supply = <&vdd_sd_dv>;
> + ti,driver-strength-ohm = <50>;
> + disable-wp;
> + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
> + cd-debounce-delay-ms = <100>;
> + ti,fails-without-test-cd;
> + status = "okay";
> +};
> +
> +&sdhci2 {
> + vmmc-supply = <&wlan_en>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
> + bus-width = <4>;
> + non-removable;
> + ti,fails-without-test-cd;
> + cap-power-off-card;
> + keep-power-in-suspend;
> + ti,driver-strength-ohm = <50>;
> + assigned-clocks = <&k3_clks 157 158>;
> + assigned-clock-parents = <&k3_clks 157 160>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + wlcore: wlcore at 2 {
> + compatible = "ti,wl1807";
> + reg = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_wlirq_pins_default>;
> + interrupt-parent = <&main_gpio0>;
> + interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
> + };
> +};
> +
> +&main_uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&console_pins_default>;
> + status = "okay";
> +};
> +
> +&main_uart1 {
> + /* Main UART1 is used by TIFS firmware */
> + status = "reserved";
> +};
> +
> +&main_uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mikrobus_uart_pins_default>;
> + status = "okay";
> +};
> +
> +&main_uart6 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_debug_uart_pins_default>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
> new file mode 100644
> index 000000000000..af6511be528c
> --- /dev/null
> +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * https://beagleboard.org/play
> + *
> + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
> + */
> +
> +#include "k3-am625-beagleplay.dts"
> +#include "k3-am625-beagleplay-ddr4-1600MTs.dtsi"
> +#include "k3-am62-ddr.dtsi"
> +
> +#include "k3-am625-beagleplay-u-boot.dtsi"
> +
> +/ {
> + aliases {
> + remoteproc0 = &sysctrler;
> + remoteproc1 = &a53_0;
> + };
> +
> +
> + a53_0: a53 at 0 {
> + compatible = "ti,am654-rproc";
> + reg = <0x00 0x00a90000 0x00 0x10>;
> + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
> + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
> + resets = <&k3_reset 135 0>;
> + clocks = <&k3_clks 61 0>;
> + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
> + assigned-clock-parents = <&k3_clks 61 2>;
> + assigned-clock-rates = <200000000>, <1250000000>;
> + ti,sci = <&dmsc>;
> + ti,sci-proc-id = <32>;
> + ti,sci-host-id = <10>;
> + bootph-pre-ram;
> + };
> +
> + dm_tifs: dm-tifs {
> + compatible = "ti,j721e-dm-sci";
> + ti,host-id = <36>;
> + ti,secure-host;
> + mbox-names = "rx", "tx";
> + mboxes= <&secure_proxy_main 22>,
> + <&secure_proxy_main 23>;
> + bootph-pre-ram;
> + };
> +};
> +
> +&dmsc {
> + mboxes= <&secure_proxy_main 0>,
> + <&secure_proxy_main 1>,
> + <&secure_proxy_main 0>;
> + mbox-names = "rx", "tx", "notify";
> + ti,host-id = <35>;
> + ti,secure-host;
> +};
> +
> +&mcu_esm {
> + bootph-pre-ram;
> +};
> +
> +&secure_proxy_sa3 {
> + bootph-pre-ram;
> + /* We require this for boot handshake */
> + status = "okay";
> +};
> +
> +&cbass_main {
> + sysctrler: sysctrler {
> + compatible = "ti,am654-system-controller";
> + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
> + mbox-names = "tx", "rx", "boot_notify";
> + bootph-pre-ram;
> + };
> +};
> +
> +&main_esm {
> + bootph-pre-ram;
> +};
> +
> +&main_pktdma {
> + ti,sci = <&dm_tifs>;
> +};
> +
> +&main_bcdma {
> + ti,sci = <&dm_tifs>;
> +};
> diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
> index 105e741995ed..6ac4e65f5afc 100644
> --- a/board/ti/am62x/MAINTAINERS
> +++ b/board/ti/am62x/MAINTAINERS
> @@ -6,3 +6,10 @@ F: board/ti/am62x/
> F: include/configs/am62x_evm.h
> F: configs/am62x_evm_r5_defconfig
> F: configs/am62x_evm_a53_defconfig
> +
> +BEAGLEPLAY BOARD
> +M: Nishanth Menon <nm at ti.com>
> +M: Robert Nelson <robertcnelson at gmail.com>
> +M: Tom Rini <trini at konsulko.com>
> +S: Maintained
> +N: beagleplay
> --
> 2.40.0
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