[PATCH v6 0/4] arch: riscv: jh7110: Correctly zero L2 LIM

Shengyu Qu wiagn233 at outlook.com
Thu Aug 24 18:25:17 CEST 2023

This series is the sixth version of Bo Gan's L2 LIM series.

Background information:
 JH7110 SPL runs in L2 LIM (2M in size mapped at 0x8000000). It
 consists of 16 0x20000 sized regions, each one can be used as
 either L2 cache way or SRAM (not both). From top to bottom, there're
 ways 0-15. The way 0 is always enabled, at most 0x1e0000 can be used.

In SPL, we don't enable any cache ways, thus all 15 (except way 0)
ways can be used. However, due to HW requirement, we must zero the
LIM before use. This is because ECC is applied to LIM, and if not
cleared first, the ECC part is invalid, which can trigger ECC errors
when reading/writing data.

There are several issues currently. We clear L2 LIM from __bss_end
to 0x81FFFFF in `harts_early_init`. This is wrong because:

 1. Each hart (in the middle of a function call) overwriting its own
    stack and other harts' stacks.
    (data-race and data-corruption)
 2. Lottery winner hart can be doing `board_init_f_init_reserve`,
    while other harts're in the middle of zeroing L2 LIM.

To fix this, we split the job, such that there's one and only one
owner of zeroing a specific region (No data-race). A new SPL config
option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing
to happen in the same code path. (much easier to reason about).

Besides, currently we use DDR ram for SPL malloc arena on Visionfive 2
board in defconfig, but it's also possible to use L2 LIM as SPL malloc
arena. To avoid triggering ECC error in this scenario, we add support
on JH7110 as default.

Changes since v1:
 - Separate single patch into several patches

Changes since v2:

Changes since v3:
 - Revert v3's fix since original implementation is actually right

Changes since v4:
 - Remove already merged patches

Changes since v5:
 - Fix whitespace in patch 1
 - Disable SYS_MALLOC_CLEAR_ON_INIT by default on Visionfive 2

Shengyu Qu (4):
  dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
  riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
  configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default

 Kconfig                                | 11 +++++++++++
 arch/riscv/cpu/jh7110/Kconfig          |  1 +
 common/dlmalloc.c                      |  6 +++---
 configs/starfive_visionfive2_defconfig |  2 ++
 4 files changed, 17 insertions(+), 3 deletions(-)


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