[PATCH 0/7] spi-nor: Add parallel and stacked memories support

[Tom Rini]

On Wed, Dec 06, 2023 at 06:58:14PM +0530, Jagan Teki wrote:
> On Wed, Dec 6, 2023 at 6:11 PM Michal Simek <michal.simek at amd.com> wrote:
> >
> >
> >
> > On 12/6/23 13:24, Jagan Teki wrote:
> > > On Fri, Aug 18, 2023 at 9:51 AM Ashok Reddy Soma
> > > <ashok.reddy.soma at amd.com> wrote:
> > >>
> > >> This series adds support for Xilinx qspi parallel and stacked memeories.
> > >>
> > >> In parallel mode, the current implementation assumes that a maximum of
> > >> two flashes are connected. The QSPI controller splits the data evenly
> > >> between both the flashes so, both the flashes that are connected in
> > >> parallel mode should be identical.
> > >> During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
> > >> nor->flags.
> > >>
> > >> In stacked mode the current implementation assumes that a maximum of two
> > >> flashes are connected and both the flashes are of same make but can
> > >> differ in sizes. So, except the sizes all other flash parameters of both
> > >> the flashes are identical
> > >>
> > >> Spi-nor will pass on the appropriate flash select flag to low level
> > >> driver, and it will select pass all the data to that particular flash.
> > >>
> > >> Write operation in parallel mode are performed in page size * 2 chunks as
> > >> each write operation results in writing both the flashes. For doubling
> > >> the address space each operation is performed at addr/2 flash offset,
> > >> where addr is the address specified by the user.
> > >>
> > >> Similarly for read and erase operations it will read from both flashes,
> > >> so size and offset are divided by 2 and send to flash.
> > >>
> > >>
> > >>
> > >> Ashok Reddy Soma (7):
> > >>    dm: core: support reading a single indexed u64 value
> > >>    mtd: spi-nor: Add parallel and stacked memories support
> > >>    mtd: spi-nor: Add parallel memories support for read_sr and read_fsr
> > >>    mtd: spi-nor: Add parallel and stacked memories support in read_bar
> > >>      and write_bar
> > >>    spi: spi-uclass: Read chipselect and restrict capabilities
> > >>    spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver
> > >>    spi: zynq_qspi: Add parallel memories support in QSPI driver
> > >
> > > This set is a bit hard to go. We need to Sync the Linux SPI-NOR tree
> > > and let Linux approve the parallel and stacked otherwise it is very
> > > difficult to maintain.
> >
> > Linux thread is here and it is pretty close to be merged.
> > https://lore.kernel.org/all/20231125092137.2948-1-amit.kumar-mahapatra@amd.com/
> >
> > DT binding is already approved but have no clue how big effort is to synchronize
> > it. When was it synchronized last time?
> 
> It wasn't. U-Boot spinor has its own and makes changes accordingly. It
> would be better to sync the Linux. This is what I'm referring to here.

Is anyone actively working on that? Under the assumption that no one is,
I really don't want to block all progress in this subsystem until a new
person steps up to start reworking everything.

-- 
Tom
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