[PATCH 1/2] clk: Check that composite clock's div has set_rate()

[Sean Anderson]

On 12/5/23 18:23, Igor Prusov wrote:
> It's possible for composite clocks to have a divider that does not
> implement set_rate() operation. For example, sandbox_clk_composite()
> registers composite clock with a divider that only has get_rate().
> Currently clk_composite_set_rate() only checks thate rate_ops are
> present, so for sandbox it will cause NULL dereference during
> clk_set_rate().
> 
> This patch adds rate_ops->set_rate check tp clk_composite_set_rate().
> 
> Signed-off-by: Igor Prusov <ivprusov at salutedevices.com>
> ---
> 
>   drivers/clk/clk-composite.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
> index 6eb2b8133a..d2e5a1ae40 100644
> --- a/drivers/clk/clk-composite.c
> +++ b/drivers/clk/clk-composite.c
> @@ -66,7 +66,7 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
>   	const struct clk_ops *rate_ops = composite->rate_ops;
>   	struct clk *clk_rate = composite->rate;
>   
> -	if (rate && rate_ops)
> +	if (rate && rate_ops && rate_ops->set_rate)
>   		return rate_ops->set_rate(clk_rate, rate);
>   	else
>   		return clk_get_rate(clk);

Reviewed-by: Sean Anderson <seanga2 at gmail.com>