[PATCH 3/5] andes: cpu: Enable memboost feature

[Leo Yu-Chi Liang]

Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
 arch/riscv/cpu/andesv5/cpu.c            | 7 +++++++
 arch/riscv/include/asm/arch-andes/csr.h | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 50cd31905d..c9288dcb51 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
 	/* Enable I/D-cache in SPL */
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
 		unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+		unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
 
 		mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \
+				MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+				MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
 
 	if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
 		mcache_ctl |= MCACHE_CTL_IC_EN;
@@ -51,4 +54,8 @@ void harts_early_init(void)
 			while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
 		}
 	}
+		mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+		csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
+	}
 }
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 93aa8b2343..755504c3c4 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -20,9 +20,15 @@
 #define MCACHE_CTL_IC_EN		BIT(0)
 #define MCACHE_CTL_DC_EN		BIT(1)
 #define MCACHE_CTL_CCTL_SUEN		BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN	BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN	BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN	BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN	BIT(15)
 #define MCACHE_CTL_DC_COHEN		BIT(19)
 #define MCACHE_CTL_DC_COHSTA		BIT(20)
 
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN	BIT(8)
 
 #define CCTL_L1D_WBINVAL_ALL 6
 
-- 
2.34.1