[RFC PATCH] riscv: cpu: check U-Mode before counteren write

Leo Liang ycliang at andestech.com
Wed Feb 1 07:52:29 CET 2023

On Wed, Dec 14, 2022 at 08:58:43AM +0300, Nikita Shubin wrote:
> From: Nikita Shubin <n.shubin at yadro.com>
> The Priv ISA states:
> "In systems without U-mode, the mcounteren register should
> not exist."
> Check U-Mode is present in MISA before writing to counteren, otherwise
> we endup with Illegal Instruction exception on systems without U-Mode.
> Also make checking MISA default for M-Mode.
> Signed-off-by: Nikita Shubin <n.shubin at yadro.com>
> ---
> This seems obvious at first glance, but i've never seen 'u' extension 
> enywhere in "riscv,isa" device tree property, even qemu doesn't set this, 
> and if we simply enable this check - this will break existing board for sure.
> We can rely on MISA completely if we are in M-Mode, as we currently check only
> 'd', 'f' and 'u', which are standart and nothing fancy.
> ---
>  arch/riscv/cpu/cpu.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>

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