[RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC
Eugen Hristev
eugen.hristev at collabora.com
Thu Feb 2 15:06:11 CET 2023
On 1/26/23 00:27, Jagan Teki wrote:
> This initial version supports CPU, dma, interrupts, timers, UART and
> SDHCI (everything necessary to boot Linux on this system on chip) as
> well as Ethernet, I2C, PWM and SPI.
>
> The DT is split into rk3588 and rk3588s, which is a reduced version
> (i.e. with less peripherals) of the former.
>
> commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
> SoC")
> commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")
>
> Signed-off-by: Jianqun Xu <jay.xu at rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> Signed-off-by: Jagan Teki <jagan at edgeble.ai>
[snip]
> +
> + cru: clock-controller at fd7c0000 {
> + compatible = "rockchip,rk3588-cru";
> + reg = <0x0 0xfd7c0000 0x0 0x5c000>;
> + assigned-clocks =
> + <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
> + <&cru PLL_NPLL>, <&cru PLL_GPLL>,
> + <&cru ACLK_CENTER_ROOT>,
> + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
> + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
> + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
Hi Jagan,
This clock PCLK_PMU0_ROOT is assigned here a clock rate (100 Mhz), but
your patch clk: rockchip: Add rk3588 clk support , in function
rk3588_clk_set_rate , does not take into account the PCLK_PMU0_ROOT ,
hence there is an error printed :
rk3588_clk_set_rate(clk=37fc28, rate=100000000): unknown clock id=646
(switch statement exits on default branch )
Could you have a look please?
Thanks,
Eugen
> + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
> + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
> + <&cru CLK_GPU>;
> + assigned-clock-rates =
> + <100000000>, <786432000>,
> + <850000000>, <1188000000>,
> + <702000000>,
> + <400000000>, <500000000>,
> + <800000000>, <100000000>,
> + <400000000>, <100000000>,
> + <200000000>, <500000000>,
> + <375000000>, <150000000>,
> + <200000000>;
> + rockchip,grf = <&php_grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
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