[PATCH v2 11/16] board: tegra124: switch to updated pre-dm i2c write
Svyatoslav Ryhel
clamor95 at gmail.com
Thu Feb 2 19:13:52 CET 2023
Configure PMIC for early stages using updated i2c write.
Signed-off-by: Svyatoslav Ryhel <clamor95 at gmail.com>
---
board/nvidia/venice2/as3722_init.c | 65 ++++++++++++--------
board/nvidia/venice2/as3722_init.h | 43 -------------
board/toradex/apalis-tk1/as3722_init.c | 85 ++++++++++++++------------
board/toradex/apalis-tk1/as3722_init.h | 40 ------------
4 files changed, 88 insertions(+), 145 deletions(-)
delete mode 100644 board/nvidia/venice2/as3722_init.h
delete mode 100644 board/toradex/apalis-tk1/as3722_init.h
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
index ba676547d3..395bdd99c7 100644
--- a/board/nvidia/venice2/as3722_init.c
+++ b/board/nvidia/venice2/as3722_init.c
@@ -9,25 +9,42 @@
#include <asm/io.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
-#include "as3722_init.h"
-/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+/* AS3722-PMIC-specific early init regs */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_I2C_ADDR 0x80
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
-}
+#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
+#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
+#define AS3722_SDCONTROL_REG 0x4D
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG 0x4E
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
-}
+#if defined(CONFIG_TARGET_VENICE2)
+#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#else /* TK1 or Nyan-Big */
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
+#endif
+#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
+
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
+#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+#endif
+
+#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
void pmic_enable_cpu_vdd(void)
{
@@ -37,8 +54,8 @@ void pmic_enable_cpu_vdd(void)
/* Set up VDD_CORE, for boards where OTP is incorrect*/
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD1VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -51,8 +68,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD0VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -64,8 +81,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD6VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -77,8 +94,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.2V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_LDO2VOLTAGE_DATA);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -93,8 +110,8 @@ void pmic_enable_cpu_vdd(void)
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_LDO6VOLTAGE_DATA);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
deleted file mode 100644
index 17e7d76ae7..0000000000
--- a/board/nvidia/venice2/as3722_init.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* AS3722-PMIC-specific early init regs */
-
-#define AS3722_I2C_ADDR 0x80
-
-#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
-#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
-#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
-#define AS3722_SDCONTROL_REG 0x4D
-
-#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
-#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
-#define AS3722_LDCONTROL_REG 0x4E
-
-#if defined(CONFIG_TARGET_VENICE2)
-#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
-#else /* TK1 or Nyan-Big */
-#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
-#endif
-#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
-
-#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
-#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
-#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
-#endif
-
-#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
-#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
-
-#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
-#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
-
-#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
-#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
-
-#define I2C_SEND_2_BYTES 0x0A02
-
-void pmic_enable_cpu_vdd(void);
diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c
index 68169f5548..e9bd1028be 100644
--- a/board/toradex/apalis-tk1/as3722_init.c
+++ b/board/toradex/apalis-tk1/as3722_init.c
@@ -8,25 +8,40 @@
#include <asm/io.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
-#include "as3722_init.h"
-/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+/* AS3722-PMIC-specific early init regs */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_I2C_ADDR 0x80
- writel(addr, ®->cmd_addr0);
- writel(config, ®->cnfg);
-}
+#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
+#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
+#define AS3722_SDCONTROL_REG 0x4D
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
+#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
+#define AS3722_LDCONTROL_REG 0x4E
- writel(data, ®->cmd_data1);
- writel(config, ®->cnfg);
-}
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
void pmic_enable_cpu_vdd(void)
{
@@ -36,8 +51,8 @@ void pmic_enable_cpu_vdd(void)
/* Set up VDD_CORE, for boards where OTP is incorrect*/
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD1VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -49,23 +64,17 @@ void pmic_enable_cpu_vdd(void)
* Make sure all non-fused regulators are down.
* That way we're in known state after software reboot from linux
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0003);
udelay(10 * 1000);
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0004);
udelay(10 * 1000);
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001b);
udelay(10 * 1000);
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0014);
udelay(10 * 1000);
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001a);
udelay(10 * 1000);
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0019);
udelay(10 * 1000);
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
@@ -73,8 +82,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD0VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -86,8 +95,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_SD6VOLTAGE_DATA);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -99,8 +108,8 @@ void pmic_enable_cpu_vdd(void)
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.2V, then enable the VDD regulator.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_LDO2VOLTAGE_DATA);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -115,8 +124,8 @@ void pmic_enable_cpu_vdd(void)
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_LDO1VOLTAGE_DATA);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
@@ -131,8 +140,8 @@ void pmic_enable_cpu_vdd(void)
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
- tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ tegra_i2c_ll_write(AS3722_I2C_ADDR,
+ AS3722_LDO6VOLTAGE_DATA);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
diff --git a/board/toradex/apalis-tk1/as3722_init.h b/board/toradex/apalis-tk1/as3722_init.h
deleted file mode 100644
index 99836de966..0000000000
--- a/board/toradex/apalis-tk1/as3722_init.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2012-2016 Toradex, Inc.
- */
-
-/* AS3722-PMIC-specific early init regs */
-
-#define AS3722_I2C_ADDR 0x80
-
-#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
-#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
-#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
-#define AS3722_SDCONTROL_REG 0x4D
-
-#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
-#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
-#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
-#define AS3722_LDCONTROL_REG 0x4E
-
-#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
-#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
-
-#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
-#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
-
-#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
-#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
-
-#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
-#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
-
-#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
-#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
-
-#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
-#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
-
-#define I2C_SEND_2_BYTES 0x0A02
-
-void pmic_enable_cpu_vdd(void);
--
2.37.2
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