[PATCH v2 100/169] Correct SPL uses of IMX8M
Simon Glass
sjg at chromium.org
Sun Feb 5 23:40:09 CET 2023
This converts 3 usages of this option to the non-SPL form, since there is
no SPL_IMX8M defined in Kconfig
Signed-off-by: Simon Glass <sjg at chromium.org>
---
(no changes since v1)
arch/arm/mach-imx/imx_bootaux.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 1a3e538c4fa..433c1f80cee 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -15,7 +15,7 @@
#include <cpu_func.h>
/* Just to avoid build error */
-#if CONFIG_IS_ENABLED(IMX8M)
+#if IS_ENABLED(CONFIG_IMX8M)
#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
#define SRC_M4_ENABLE_MASK BIT(0)
#define SRC_M4_REG_OFFSET 0
@@ -128,7 +128,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
flush_dcache_all();
/* Enable M4 */
- if (CONFIG_IS_ENABLED(IMX8M)) {
+ if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -143,7 +143,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
struct arm_smccc_res res;
unsigned int val;
- if (CONFIG_IS_ENABLED(IMX8M)) {
+ if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
--
2.39.1.519.gcb327c4b5f-goog
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