[PATCH v2 08/10] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Marek Vasut
marex at denx.de
Thu Feb 9 22:50:46 CET 2023
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Reviewed-by: Ramon Fried <rfried.dev at gmail.com>
Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro at collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin at leica-geosystems.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Joe Hershberger <joe.hershberger at ni.com>
Cc: Lukasz Majewski <lukma at denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler at toradex.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Michael Trimarchi <michael at amarulasolutions.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Ramon Fried <rfried.dev at gmail.com>
Cc: Sean Anderson <seanga2 at gmail.com>
Cc: Stefano Babic <sbabic at denx.de>
Cc: Tim Harvey <tharvey at gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai at amarulasolutions.com>
Cc: u-boot at lists.denx.de
---
V2: - Add RB from Ramon
- Handle RGMII_ID/RGMII_RXID/RGMII_TXID just like plain RGMII
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 ++++-
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 40 ++++++++++++++++++++++
drivers/net/dwc_eth_qos_imx.c | 4 +++
3 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 1559bf6d218..1818b459fa6 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -89,7 +89,13 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_ARMV8_PSCI /* Final jump location */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 494bfbedc8c..6d3539ec982 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -15,6 +15,7 @@
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -872,6 +873,45 @@ int set_clk_eqos(enum enet_freq type)
return 0;
}
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ clrbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
#endif
#ifdef CONFIG_FEC_MXC
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index fb4e6d38e24..f565a5fd21a 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -55,6 +55,10 @@ static int eqos_probe_resources_imx(struct udevice *dev)
return -EINVAL;
}
+ ret = board_interface_eth_init(dev, interface);
+ if (ret)
+ return -EINVAL;
+
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
--
2.39.1
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