[PATCH v2 13/14] rockchip: Enable bootstage on rockpro64

Andrew Abbott andrew at mirx.dev
Sun Feb 12 00:29:23 CET 2023

On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we can collect
> timing from TPL.
> For the stash region, use a portion of SRAM, 64KB below the stack top.
> This allows the TPL image to be up to nearly 120KB (it is typically about
> 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> region.
> Signed-off-by: Simon Glass <sjg at chromium.org>

> diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> index 5b8d678f6bb..2f1ae156bd4 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
> CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
> @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800

Building from master commit a1e6b529e57c622e862e93fa6da03d9504565089 and copying u-boot-rockchip.bin to an SD card and booting from that on a RockPRO64 v2.1, I don't get past this:
(dirty because building on NixOS applies some patches)

>U-Boot TPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00)
>Channel 0: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>Channel 1: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>256B stride
>lpddr4_set_rate: change freq to 800MHz 1, 0
>Trying to boot from BOOTROM
>Returning to boot ROM...
>U-Boot SPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00 +0000)
>Trying to boot from MMC2

I bisected down to this patch. If I disable CONFIG_BOOTSTATE, I can boot. Is there something I need to do to successfully boot with bootstate enabled?

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