[PATCH 1/5] arm: ls1012: remove ls1012aqds

Peng Fan (OSS) peng.fan at oss.nxp.com
Sun Feb 12 11:17:16 CET 2023


From: Peng Fan <peng.fan at nxp.com>

This is NXP internal validation board, no longer support it.

Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 arch/arm/Kconfig                              |  14 -
 arch/arm/cpu/armv8/Kconfig                    |   2 +-
 .../cpu/armv8/fsl-layerscape/doc/README.qspi  |   1 -
 board/freescale/ls1012aqds/Kconfig            |  80 -----
 board/freescale/ls1012aqds/MAINTAINERS        |   9 -
 board/freescale/ls1012aqds/Makefile           |   8 -
 board/freescale/ls1012aqds/README             |  59 ----
 board/freescale/ls1012aqds/eth.c              | 309 ------------------
 board/freescale/ls1012aqds/ls1012aqds.c       | 293 -----------------
 board/freescale/ls1012aqds/ls1012aqds_pfe.h   |  44 ---
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |  34 --
 configs/ls1012aqds_qspi_defconfig             |  95 ------
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |  87 -----
 configs/ls1012aqds_tfa_defconfig              |  94 ------
 include/configs/ls1012aqds.h                  | 109 ------
 15 files changed, 1 insertion(+), 1237 deletions(-)
 delete mode 100644 board/freescale/ls1012aqds/Kconfig
 delete mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 delete mode 100644 board/freescale/ls1012aqds/Makefile
 delete mode 100644 board/freescale/ls1012aqds/README
 delete mode 100644 board/freescale/ls1012aqds/eth.c
 delete mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
 delete mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
 delete mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 delete mode 100644 configs/ls1012aqds_qspi_defconfig
 delete mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
 delete mode 100644 configs/ls1012aqds_tfa_defconfig
 delete mode 100644 include/configs/ls1012aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd7fffcce0b..752e379e3c1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1482,19 +1482,6 @@ config TARGET_POPLAR
 	  making it capable of running any commercial set-top solution based on
 	  Linux or Android.
 
-config TARGET_LS1012AQDS
-	bool "Support ls1012aqds"
-	select ARCH_LS1012A
-	select ARM64
-	select ARCH_SUPPORT_TFABOOT
-	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
-	help
-	  Support for Freescale LS1012AQDS platform.
-	  The LS1012A Development System (QDS) is a high-performance
-	  development platform that supports the QorIQ LS1012A
-	  Layerscape Architecture processor.
-
 config TARGET_LS1012ARDB
 	bool "Support ls1012ardb"
 	select ARCH_LS1012A
@@ -2283,7 +2270,6 @@ source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1046afrwy/Kconfig"
-source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/lx2160a/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 1305238c9d2..74fd13b95f8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -116,7 +116,7 @@ config PSCI_RESET
 		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
-		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
+		   !TARGET_LS1012A2G5RDB && \
 		   !TARGET_LS1012AFRWY && \
 		   !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
index de86f4b3079..563e73023ca 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.qspi
@@ -5,7 +5,6 @@ QSPI Boot source support Overview
 	2. LS2080A
 		LS2080AQDS
 	3. LS1012A
-		LS1012AQDS
 		LS1012ARDB
 	4. LS1046A
 		LS1046AQDS
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
deleted file mode 100644
index 991ba6044db..00000000000
--- a/board/freescale/ls1012aqds/Kconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-if TARGET_LS1012AQDS
-
-config SYS_BOARD
-	default "ls1012aqds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_SOC
-	default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
-	default "ls1012aqds"
-
-config SYS_LS_PPA_FW_ADDR
-        hex "PPA Firmware Addr"
-        default 0x40400000
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
-	hex "PPA Firmware HDR Addr"
-	default 0x40680000
-
-config SYS_LS_PFE_ESBC_ADDR
-	hex "PFE Firmware HDR Addr"
-	default 0x40700000
-
-config SYS_LS_PFE_ESBC_LENGTH
-	hex "length of PFE Firmware HDR"
-	default 0xc00
-endif
-
-if FSL_PFE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select PHYLIB
-	imply PHY_VITESSE
-	imply PHY_REALTEK
-	imply PHY_AQUANTIA
-	imply PHYLIB_10G
-
-config PFE_RGMII_RESET_WA
-	def_bool y
-
-config SYS_LS_PFE_FW_ADDR
-	hex "Flash address of PFE firmware"
-	default 0x40a00000
-
-config SYS_LS_PFE_FW_LENGTH
-	hex "length of PFE firmware"
-	default 0x300000
-
-config DDR_PFE_PHYS_BASEADDR
-	hex "PFE DDR physical base address"
-	default 0x03800000
-
-config DDR_PFE_BASEADDR
-	hex "PFE DDR base address"
-	default 0x83800000
-
-config PFE_EMAC1_PHY_ADDR
-	hex "PFE DDR base address"
-	default 0x1e
-
-config PFE_EMAC2_PHY_ADDR
-	hex "PFE DDR base address"
-	default 0x1
-
-config PFE_SGMII_2500_PHY1_ADDR
-	hex "PFE DDR base address"
-	default 0x1
-
-config PFE_SGMII_2500_PHY2_ADDR
-	hex "PFE DDR base address"
-	default 0x2
-
-endif
-
-endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
deleted file mode 100644
index c1bb8d51508..00000000000
--- a/board/freescale/ls1012aqds/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-LS1012AQDS BOARD
-M:	Rajesh Bhagat <rajesh.bhagat at nxp.com>
-M:	Pramod Kumar <pramod.kumar_1 at nxp.com>
-S:	Maintained
-F:	board/freescale/ls1012aqds/
-F:	include/configs/ls1012aqds.h
-F:	configs/ls1012aqds_qspi_defconfig
-F:	configs/ls1012aqds_tfa_defconfig
-F:	configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
deleted file mode 100644
index 5aba9caf927..00000000000
--- a/board/freescale/ls1012aqds/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright 2016 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:      GPL-2.0+
-#
-
-obj-y += ls1012aqds.o
-obj-$(CONFIG_FSL_PFE) += eth.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
deleted file mode 100644
index c1956f9fd78..00000000000
--- a/board/freescale/ls1012aqds/README
+++ /dev/null
@@ -1,59 +0,0 @@
-Overview
---------
-QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
-development platform, with a complete debugging environment.
-The LS1012AQDS board supports the QorIQ LS1012A processor and is
-optimized to support the high-bandwidth DDR3L memory and
-a full complement of high-speed SerDes ports.
-
-LS1012A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
-SoC overview.
-
-LS1012AQDS board Overview
------------------------
- - SERDES Connections, 4 lanes supporting:
-      - PCI Express - 3.0
-      - SGMII, SGMII 2.5
-      - SATA 3.0
- - DDR Controller
-     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
- - QSPI Controller
-     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
-       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
-       emulator
- - USB 3.0
-    - One USB 3.0 controller with integrated PHY
-    - One high-speed USB 3.0 port
- - USB 2.0
-    - One USB 2.0 controller with ULPI interface
- - Two enhanced secure digital host controllers:
-    - SDHC1 controller can be connected to onboard SDHC connector
-    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
- - 2 I2C controllers
- - One SATA onboard connectors
- - UART
- - 5 SAI
-    - One SAI port with audio codec SGTL5000:
-	• Provides MIC bias
-	• Provides headphone and line output
-    - One SAI port terminated at 2x6 header
-    - Three SAI Tx/Rx ports terminated at 2x3 headers
- - ARM JTAG support
-
-Booting Options
----------------
-a) QSPI Flash Emu Boot
-b) QSPI Flash 1
-c) QSPI Flash 2
-
-QSPI flash map
---------------
-Images		| Size	|QSPI Flash Address
-------------------------------------------
-RCW + PBI	| 1MB	| 0x4000_0000
-U-boot		| 1MB	| 0x4010_0000
-U-boot Env	| 1MB	| 0x4020_0000
-PPA FIT image	| 2MB	| 0x4050_0000
-Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
deleted file mode 100644
index 38267acedde..00000000000
--- a/board/freescale/ls1012aqds/eth.c
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <asm/types.h>
-#include <fsl_dtsec.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/config.h>
-#include <asm/arch-fsl-layerscape/immap_lsch2.h>
-#include <asm/arch/fsl_serdes.h>
-#include <linux/delay.h>
-#include "../common/qixis.h"
-#include <net/pfe_eth/pfe_eth.h>
-#include <dm/platform_data/pfe_dm_eth.h>
-#include "ls1012aqds_qixis.h"
-
-#define EMI_NONE	0xFF
-#define EMI1_RGMII	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT2	3
-
-#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
-#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
-
-static const char * const mdio_names[] = {
-	"NULL",
-	"LS1012AQDS_MDIO_RGMII",
-	"LS1012AQDS_MDIO_SLOT1",
-	"LS1012AQDS_MDIO_SLOT2",
-	"NULL",
-};
-
-static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct ls1012aqds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static void ls1012aqds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-
-	if (muxval < 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct ls1012aqds_mdio *priv = bus->priv;
-
-	ls1012aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				 int regnum, u16 value)
-{
-	struct ls1012aqds_mdio *priv = bus->priv;
-
-	ls1012aqds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int ls1012aqds_mdio_reset(struct mii_dev *bus)
-{
-	struct ls1012aqds_mdio *priv = bus->priv;
-
-	if (priv->realbus->reset)
-		return priv->realbus->reset(priv->realbus);
-	else
-		return -1;
-}
-
-static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct ls1012aqds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate ls1012aqds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate ls1012aqds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = ls1012aqds_mdio_read;
-	bus->write = ls1012aqds_mdio_write;
-	bus->reset = ls1012aqds_mdio_reset;
-	sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-	return mdio_register(bus);
-}
-
-int pfe_eth_board_init(struct udevice *dev)
-{
-	static int init_done;
-	struct mii_dev *bus;
-	static const char *mdio_name;
-	struct pfe_mdio_info mac_mdio_info;
-	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
-	u8 data8;
-	struct pfe_eth_dev *priv = dev_get_priv(dev);
-
-	int srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	ls1012aqds_mux_mdio(EMI1_SLOT1);
-
-	if (!init_done) {
-		mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
-		mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
-
-		bus = pfe_mdio_init(&mac_mdio_info);
-		if (!bus) {
-			printf("Failed to register mdio\n");
-			return -1;
-		}
-		init_done = 1;
-	}
-
-	if (priv->gemac_port) {
-		mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
-		mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
-
-		bus = pfe_mdio_init(&mac_mdio_info);
-		if (!bus) {
-			printf("Failed to register mdio\n");
-			return -1;
-		}
-	}
-
-	switch (srds_s1) {
-	case 0x3508:
-		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
-#ifdef CONFIG_PFE_RGMII_RESET_WA
-		/*
-		 * Work around for FPGA registers initialization
-		 * This is needed for RGMII to work.
-		 */
-		printf("Reset RGMII WA....\n");
-		data8 = QIXIS_READ(rst_frc[0]);
-		data8 |= 0x2;
-		QIXIS_WRITE(rst_frc[0], data8);
-		data8 = QIXIS_READ(rst_frc[0]);
-
-		data8 = QIXIS_READ(res8[6]);
-		data8 |= 0xff;
-		QIXIS_WRITE(res8[6], data8);
-		data8 = QIXIS_READ(res8[6]);
-#endif
-	if (priv->gemac_port) {
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
-		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
-		    < 0) {
-			printf("Failed to register mdio for %s\n", mdio_name);
-		}
-
-		/* MAC2 */
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
-		bus = miiphy_get_dev_by_name(mdio_name);
-		pfe_set_mdio(priv->gemac_port, bus);
-		pfe_set_phy_address_mode(priv->gemac_port,
-					 CONFIG_PFE_EMAC2_PHY_ADDR,
-					 PHY_INTERFACE_MODE_RGMII);
-
-	} else {
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
-		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
-		< 0) {
-			printf("Failed to register mdio for %s\n", mdio_name);
-		}
-
-		/* MAC1 */
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
-		bus = miiphy_get_dev_by_name(mdio_name);
-		pfe_set_mdio(priv->gemac_port, bus);
-		pfe_set_phy_address_mode(priv->gemac_port,
-					 CONFIG_PFE_EMAC1_PHY_ADDR,
-					 PHY_INTERFACE_MODE_SGMII);
-	}
-
-		break;
-
-	case 0x2205:
-		printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
-		/*
-		 * Work around for FPGA registers initialization
-		 * This is needed for RGMII to work.
-		 */
-		printf("Reset SLOT1 SLOT2....\n");
-		data8 = QIXIS_READ(rst_frc[2]);
-		data8 |= 0xc0;
-		QIXIS_WRITE(rst_frc[2], data8);
-		mdelay(100);
-		data8 = QIXIS_READ(rst_frc[2]);
-		data8 &= 0x3f;
-		QIXIS_WRITE(rst_frc[2], data8);
-
-	if (priv->gemac_port) {
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
-		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
-		< 0) {
-			printf("Failed to register mdio for %s\n", mdio_name);
-		}
-		/* MAC2 */
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
-		bus = miiphy_get_dev_by_name(mdio_name);
-		pfe_set_mdio(1, bus);
-		pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
-					 PHY_INTERFACE_MODE_2500BASEX);
-
-		data8 = QIXIS_READ(brdcfg[12]);
-		data8 |= 0x20;
-		QIXIS_WRITE(brdcfg[12], data8);
-
-	} else {
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
-		if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
-		    < 0) {
-			printf("Failed to register mdio for %s\n", mdio_name);
-		}
-
-		/* MAC1 */
-		mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
-		bus = miiphy_get_dev_by_name(mdio_name);
-		pfe_set_mdio(0, bus);
-		pfe_set_phy_address_mode(0,
-					 CONFIG_PFE_SGMII_2500_PHY1_ADDR,
-					 PHY_INTERFACE_MODE_2500BASEX);
-	}
-		break;
-
-	default:
-		printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
-		break;
-	}
-	return 0;
-}
-
-static struct pfe_eth_pdata pfe_pdata0 = {
-	.pfe_eth_pdata_mac = {
-		.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
-		.phy_interface = 0,
-	},
-
-	.pfe_ddr_addr = {
-		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
-		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
-	},
-};
-
-static struct pfe_eth_pdata pfe_pdata1 = {
-	.pfe_eth_pdata_mac = {
-		.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
-		.phy_interface = 1,
-	},
-
-	.pfe_ddr_addr = {
-		.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
-		.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
-	},
-};
-
-U_BOOT_DRVINFO(ls1012a_pfe0) = {
-	.name = "pfe_eth",
-	.plat = &pfe_pdata0,
-};
-
-U_BOOT_DRVINFO(ls1012a_pfe1) = {
-	.name = "pfe_eth",
-	.plat = &pfe_pdata1,
-};
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
deleted file mode 100644
index 194b5d27295..00000000000
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ /dev/null
@@ -1,293 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/cache.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#ifdef CONFIG_FSL_LS_PPA
-#include <asm/arch/ppa.h>
-#endif
-#include <asm/arch/fdt.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/soc.h>
-#include <ahci.h>
-#include <hwconfig.h>
-#include <mmc.h>
-#include <env_internal.h>
-#include <scsi.h>
-#include <fm_eth.h>
-#include <fsl_esdhc.h>
-#include <fsl_mmdc.h>
-#include <spl.h>
-#include <netdev.h>
-#include "../common/qixis.h"
-#include "ls1012aqds_qixis.h"
-#include "ls1012aqds_pfe.h"
-#include <net/pfe_eth/pfe/pfe_hw.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-
-	sw = QIXIS_READ(arch);
-	printf("Board Arch: V%d, ", sw >> 4);
-	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
-	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
-
-	if (sw & QIXIS_LBMAP_ALTBANK)
-		printf("flash: 2\n");
-	else
-		printf("flash: 1\n");
-
-	printf("FPGA: v%d (%s), build %d",
-	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
-	       (int)qixis_read_minor());
-
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-	return 0;
-}
-
-#ifdef CONFIG_TFABOOT
-int dram_init(void)
-{
-	gd->ram_size = tfa_get_dram_size();
-	if (!gd->ram_size)
-		gd->ram_size = CFG_SYS_SDRAM_SIZE;
-
-	return 0;
-}
-#else
-int dram_init(void)
-{
-	static const struct fsl_mmdc_info mparam = {
-		0x05180000,	/* mdctl */
-		0x00030035,	/* mdpdc */
-		0x12554000,	/* mdotc */
-		0xbabf7954,	/* mdcfg0 */
-		0xdb328f64,	/* mdcfg1 */
-		0x01ff00db,	/* mdcfg2 */
-		0x00001680,	/* mdmisc */
-		0x0f3c8000,	/* mdref */
-		0x00002000,	/* mdrwd */
-		0x00bf1023,	/* mdor */
-		0x0000003f,	/* mdasp */
-		0x0000022a,	/* mpodtctrl */
-		0xa1390003,	/* mpzqhwctrl */
-	};
-
-	mmdc_init(&mparam);
-	gd->ram_size = CFG_SYS_SDRAM_SIZE;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-	/* This will break-before-make MMU for DDR */
-	update_early_mmu_table();
-#endif
-
-	return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
-	fsl_lsch2_early_init_f();
-
-	return 0;
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-	u8 mux_sdhc_cd = 0x80;
-	int bus_num = 0;
-
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-	int ret;
-
-	ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-	dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
-#else
-	i2c_set_bus_num(bus_num);
-
-	i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
-#endif
-
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
-				   CONFIG_SYS_CCI400_OFFSET);
-
-	/* Set CCI-400 control override register to enable barrier
-	 * transaction */
-	if (current_el() == 3)
-		out_le32(&cci->ctrl_ord,
-			 CCI400_CTRLORD_EN_BARRIER);
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-	erratum_a010315();
-#endif
-
-#ifdef CONFIG_FSL_LS_PPA
-	ppa_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_FSL_PFE
-void board_quiesce_devices(void)
-{
-	pfe_command_stop(0, NULL);
-}
-#endif
-
-int esdhc_status_fixup(void *blob, const char *compat)
-{
-	char esdhc0_path[] = "/soc/esdhc at 1560000";
-	char esdhc1_path[] = "/soc/esdhc at 1580000";
-	u8 card_id;
-
-	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
-			 sizeof("okay"), 1);
-
-	/*
-	 * The Presence Detect 2 register detects the installation
-	 * of cards in various PCI Express or SGMII slots.
-	 *
-	 * STAT_PRS2[7:5]: Specifies the type of card installed in the
-	 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
-	 */
-	card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
-
-	/* If no adapter is installed in SDHC2, disable SDHC2 */
-	if (card_id == 0x7)
-		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
-				 sizeof("disabled"), 1);
-	else
-		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
-				 sizeof("okay"), 1);
-	return 0;
-}
-
-static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
-			      char *enet_path, char *mdio_path)
-{
-	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
-			 &prop_val.busid, PFE_PROP_LEN, 1);
-	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
-			 &prop_val.phyid, PFE_PROP_LEN, 1);
-	do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
-			 &prop_val.mux_val, PFE_PROP_LEN, 1);
-	do_fixup_by_path(set_blob, enet_path, "phy-mode",
-			 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
-	do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
-			 &prop_val.phy_mask, PFE_PROP_LEN, 1);
-	return 0;
-}
-
-static void fdt_fsl_fixup_of_pfe(void *blob)
-{
-	int i = 0;
-	struct pfe_prop_val prop_val;
-	void *l_blob = blob;
-
-	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
-	unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
-		FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	for (i = 0; i < NUM_ETH_NODE; i++) {
-		switch (srds_s1) {
-		case SERDES_1_G_PROTOCOL:
-			if (i == 0) {
-				prop_val.busid = cpu_to_fdt32(
-						ETH_1_1G_BUS_ID);
-				prop_val.phyid = cpu_to_fdt32(
-						ETH_1_1G_PHY_ID);
-				prop_val.mux_val = cpu_to_fdt32(
-						ETH_1_1G_MDIO_MUX);
-				prop_val.phy_mask = cpu_to_fdt32(
-						ETH_1G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "sgmii";
-				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
-						   ETH_1_MDIO);
-			} else {
-				prop_val.busid = cpu_to_fdt32(
-						ETH_2_1G_BUS_ID);
-				prop_val.phyid = cpu_to_fdt32(
-						ETH_2_1G_PHY_ID);
-				prop_val.mux_val = cpu_to_fdt32(
-						ETH_2_1G_MDIO_MUX);
-				prop_val.phy_mask = cpu_to_fdt32(
-						ETH_1G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "rgmii";
-				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
-						   ETH_2_MDIO);
-			}
-		break;
-		case SERDES_2_5_G_PROTOCOL:
-			if (i == 0) {
-				prop_val.busid = cpu_to_fdt32(
-						ETH_1_2_5G_BUS_ID);
-				prop_val.phyid = cpu_to_fdt32(
-						ETH_1_2_5G_PHY_ID);
-				prop_val.mux_val = cpu_to_fdt32(
-						ETH_1_2_5G_MDIO_MUX);
-				prop_val.phy_mask = cpu_to_fdt32(
-						ETH_2_5G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "2500base-x";
-				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
-						   ETH_1_MDIO);
-			} else {
-				prop_val.busid = cpu_to_fdt32(
-						ETH_2_2_5G_BUS_ID);
-				prop_val.phyid = cpu_to_fdt32(
-						ETH_2_2_5G_PHY_ID);
-				prop_val.mux_val = cpu_to_fdt32(
-						ETH_2_2_5G_MDIO_MUX);
-				prop_val.phy_mask = cpu_to_fdt32(
-						ETH_2_5G_MDIO_PHY_MASK);
-				prop_val.phy_mode = "2500base-x";
-				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
-						   ETH_2_MDIO);
-			}
-		break;
-		default:
-			printf("serdes:[%d]\n", srds_s1);
-		}
-	}
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	arch_fixup_fdt(blob);
-
-	ft_cpu_setup(blob, bd);
-	fdt_fsl_fixup_of_pfe(blob);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
deleted file mode 100644
index 5ab283ce8d5..00000000000
--- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2017 NXP
- */
-
-#define ETH_1_1G_BUS_ID		0x1
-#define ETH_1_1G_PHY_ID		0x1e
-#define ETH_1_1G_MDIO_MUX	0x2
-#define ETH_1G_MDIO_PHY_MASK	0xBFFFFFFD
-#define ETH_1_1G_PHY_MODE	"sgmii"
-#define ETH_2_1G_BUS_ID		0x1
-#define ETH_2_1G_PHY_ID		0x1
-#define ETH_2_1G_MDIO_MUX	0x1
-#define ETH_2_1G_PHY_MODE	"rgmii"
-
-#define ETH_1_2_5G_BUS_ID	0x0
-#define ETH_1_2_5G_PHY_ID	0x1
-#define ETH_1_2_5G_MDIO_MUX	0x2
-#define ETH_2_5G_MDIO_PHY_MASK	0xFFFFFFF9
-#define ETH_2_5G_PHY_MODE	"2500base-x"
-#define ETH_2_2_5G_BUS_ID	0x1
-#define ETH_2_2_5G_PHY_ID	0x2
-#define ETH_2_2_5G_MDIO_MUX	0x3
-
-#define SERDES_1_G_PROTOCOL	0x3508
-#define SERDES_2_5_G_PROTOCOL	0x2205
-
-#define PFE_PROP_LEN		4
-
-#define ETH_1_PATH		"/pfe at 04000000/ethernet at 0"
-#define ETH_1_MDIO		ETH_1_PATH "/mdio at 0"
-
-#define ETH_2_PATH		"/pfe at 04000000/ethernet at 1"
-#define ETH_2_MDIO		ETH_2_PATH "/mdio at 0"
-
-#define NUM_ETH_NODE		2
-
-struct pfe_prop_val {
-	int busid;
-	int phyid;
-	int mux_val;
-	int phy_mask;
-	char *phy_mode;
-};
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
deleted file mode 100644
index 19f522d9eaa..00000000000
--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#ifndef __LS1043AQDS_QIXIS_H__
-#define __LS1043AQDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for LS1043AQDS */
-
-/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xe0
-#define BRDCFG4_EMISEL_SHIFT		6
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66			0x0
-#define QIXIS_SYSCLK_83			0x1
-#define QIXIS_SYSCLK_100		0x2
-#define QIXIS_SYSCLK_125		0x3
-#define QIXIS_SYSCLK_133		0x4
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66			0x0
-#define QIXIS_DDRCLK_100		0x1
-#define QIXIS_DDRCLK_125		0x2
-#define QIXIS_DDRCLK_133		0x3
-
-/* BRDCFG2 - SD clock*/
-#define QIXIS_SDCLK1_100		0x0
-#define QIXIS_SDCLK1_125		0x1
-#define QIXIS_SDCLK1_165		0x2
-#define QIXIS_SDCLK1_100_SP		0x3
-
-#endif
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
deleted file mode 100644
index fcef5e5d5bb..00000000000
--- a/configs/ls1012aqds_qspi_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AQDS=y
-CONFIG_TEXT_BASE=0x40100000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x300000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-CONFIG_BOOTCOMMAND="run distro_bootcmd; run qspi_bootcmd; env exists secureboot && esbc_halt;"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SPI=y
-CONFIG_DEFAULT_SPI_BUS=1
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_SPI_MAX_HZ=1000000
-CONFIG_ENV_SPI_MODE=0x03
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PCF8563=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
deleted file mode 100644
index c2996a1372e..00000000000
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AQDS=y
-CONFIG_TFABOOT=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_NXP_ESBC=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SPI=y
-CONFIG_DEFAULT_SPI_BUS=1
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_FSL_SEC_MON_BE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PCF8563=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
deleted file mode 100644
index a1709f4525b..00000000000
--- a/configs/ls1012aqds_tfa_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=25000000
-CONFIG_TARGET_LS1012AQDS=y
-CONFIG_TFABOOT=y
-CONFIG_TEXT_BASE=0x82000000
-CONFIG_SYS_MALLOC_LEN=0x500000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x500000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
-CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
-CONFIG_AHCI=y
-CONFIG_LAYERSCAPE_NS_ACCESS=y
-CONFIG_PCIE1=y
-CONFIG_FSL_QIXIS=y
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x9fffffff
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
-# CONFIG_USE_BOOTCOMMAND is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
-CONFIG_ID_EEPROM=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_SYS_PBSIZE=532
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SPI=y
-CONFIG_DEFAULT_SPI_BUS=1
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_BUS=0
-CONFIG_ENV_SPI_MAX_HZ=1000000
-CONFIG_ENV_SPI_MODE=0x03
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SATA=y
-CONFIG_SCSI_AHCI=y
-CONFIG_SATA_CEVA=y
-CONFIG_MPC8XXX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x57
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=1
-CONFIG_SF_DEFAULT_SPEED=10000000
-# CONFIG_SPI_FLASH_BAR is not set
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FSL_PFE=y
-CONFIG_E1000=y
-CONFIG_NVME_PCI=y
-CONFIG_PCI=y
-CONFIG_PCIE_LAYERSCAPE_RC=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_PCF8563=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
deleted file mode 100644
index 35e8ff05798..00000000000
--- a/include/configs/ls1012aqds.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
- */
-
-#ifndef __LS1012AQDS_H__
-#define __LS1012AQDS_H__
-
-#include "ls1012a_common.h"
-
-/* DDR */
-#define CFG_SYS_SDRAM_SIZE		0x40000000
-
-/*
- * QIXIS Definitions
- */
-
-#ifdef CONFIG_FSL_QIXIS
-#define CFG_SYS_I2C_FPGA_ADDR	0x66
-#define QIXIS_LBMAP_BRDCFG_REG		0x04
-#define QIXIS_LBMAP_SWITCH		6
-#define QIXIS_LBMAP_MASK		0x08
-#define QIXIS_LBMAP_SHIFT		0
-#define QIXIS_LBMAP_DFLTBANK		0x00
-#define QIXIS_LBMAP_ALTBANK		0x08
-#define QIXIS_RST_CTL_RESET		0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
-#endif
-
-/*
- * I2C bus multiplexer
- */
-#define I2C_MUX_PCA_ADDR_PRI		0x77
-#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
-#define I2C_RETIMER_ADDR		0x18
-#define I2C_MUX_CH_DEFAULT		0x8
-#define I2C_MUX_CH_CH7301		0xC
-#define I2C_MUX_CH5			0xD
-#define I2C_MUX_CH7			0xF
-
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-
-/*
-* RTC configuration
-*/
-#define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
-
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR           0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
-
-#undef CFG_EXTRA_ENV_SETTINGS
-#define CFG_EXTRA_ENV_SETTINGS		\
-	"verify=no\0"				\
-	"kernel_addr=0x01000000\0"		\
-	"kernelheader_addr=0x600000\0"		\
-	"scriptaddr=0x80000000\0"		\
-	"scripthdraddr=0x80080000\0"		\
-	"fdtheader_addr_r=0x80100000\0"		\
-	"kernelheader_addr_r=0x80200000\0"	\
-	"kernel_addr_r=0x96000000\0"		\
-	"fdt_addr_r=0x90000000\0"		\
-	"load_addr=0xa0000000\0"		\
-	"kernel_size=0x2800000\0"		\
-	"kernelheader_size=0x40000\0"		\
-	"console=ttyS0,115200\0"		\
-	BOOTENV					\
-	"boot_scripts=ls1012aqds_boot.scr\0"	\
-	"boot_script_hdr=hdr_ls1012aqds_bs.out\0"	\
-	"scan_dev_for_boot_part="		\
-	     "part list ${devtype} ${devnum} devplist; "	\
-	     "env exists devplist || setenv devplist 1; "	\
-	     "for distro_bootpart in ${devplist}; do "		\
-		  "if fstype ${devtype} "			\
-		      "${devnum}:${distro_bootpart} "		\
-		      "bootfstype; then "			\
-		      "run scan_dev_for_boot; "	\
-		  "fi; "			\
-	      "done\0"				\
-	"boot_a_script="				  \
-		"load ${devtype} ${devnum}:${distro_bootpart} "  \
-			"${scriptaddr} ${prefix}${script}; "    \
-		"env exists secureboot && load ${devtype} "     \
-			"${devnum}:${distro_bootpart} "		\
-			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
-			"env exists secureboot "	\
-			"&& esbc_validate ${scripthdraddr};"    \
-		"source ${scriptaddr}\0"	  \
-	"qspi_bootcmd=echo Trying load from qspi..;"	\
-		"sf probe 0:0 && sf read $load_addr "	\
-		"$kernel_addr $kernel_size; env exists secureboot "	\
-		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
-		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
-		"bootm $load_addr#$board\0"
-
-#ifdef CONFIG_TFABOOT
-#undef QSPI_NOR_BOOTCOMMAND
-#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "\
-			     "env exists secureboot && esbc_halt;"
-#endif
-
-#include <asm/fsl_secure_boot.h>
-#endif /* __LS1012AQDS_H__ */
-- 
2.36.0



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