[PATCH v3 59/95] kconfig: Add a configuration file for nospl

[Simon Glass]

This file indicates which options are not for use in U-Boot SPL. It allows
the kconfig tool to correctly generate its output.

It was generated with

   ./tools/moveconfig.py --scan-source -u

Note that this only produces sensible results when used with the current
source code, as of this patch. Following patches adjust the code, e.g. to
drop use of CONFIG_IS_ENABLED(), so the program will not produce anything
useful when run on that version of the code.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3:
- Add DFU_VIRT FSL_ISBC_KEY_EXT GENERATE_SMBIOS_TABLE
  GMAC_ROCKCHIP I8259_PIC IMX_RDC NXP_FSPI PCI_PNP PHY_CADENCE_TORRENT
  QFW_PIO SEC_FIRMWARE_ARMV8_PSCI SPI_FLASH_BAR SPI_FLASH_MACRONIX
- Add CMD_BOOTEFI_BOOTMGR CMD_EFICONFIG CMD_PXE
- Fix move_config typo
- Add ARCH_VERSAL_NET CMD_DHCP ENV_WRITEABLE_LIST EXPO
- Add TARGET_KMCOGE5NE TARGET_KMETER1

 scripts/conf_nospl | 113 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 scripts/conf_nospl

diff --git a/scripts/conf_nospl b/scripts/conf_nospl
new file mode 100644
index 00000000000..fc9e5a93422
--- /dev/null
+++ b/scripts/conf_nospl
@@ -0,0 +1,113 @@
+# Options which are never enabled in SPL.
+
+Generally, options which have no SPL_ prefix (e.g. CONFIG_FOO) apply to all
+SPL build phases. This allows things like ARCH_ARM to propagate to all builds
+without the hassle of generating a separate SPL version fo each phase. But in
+some cases this is not wanted.
+
+This file lists options which don't have an SPL equivalent, but still should not
+be enabled in SPL builds. It is necessary since kconfig cannot tell (just by
+looking at the Kconfig description) whether it applies to Proper builds only,
+or to all builds.
+
+ACPI_PMC_SANDBOX
+ARCH_VERSAL_NET
+BINMAN_FDT
+CLK_INTEL
+CMD_BOOTEFI_BOOTMGR
+CMD_DHCP
+CMD_EFICONFIG
+CMD_MMC_RPMB
+CMD_MMC_SWRITE
+CMD_PXE
+DFU_MMC
+DFU_MTD
+DFU_NAND
+DFU_SF
+DFU_SF_PART
+DFU_VIRT
+DFU_WRITE_ALT
+DMA_LEGACY
+DM_DMA
+DM_EVENT
+DM_REGULATOR_ANATOP
+DM_REGULATOR_PBIAS
+DM_REGULATOR_STM32_VREFBUF
+DM_STDIO
+DWC_AHSATA_AHCI
+EFI_DT_FIXUP
+EFI_EBBR_2_1_CONFORMANCE
+EFI_SCROLL_ON_CLEAR_SCREEN
+EFI_UNICODE_CAPITALIZATION
+ENV_APPEND
+ENV_WRITEABLE_LIST
+EVENT_DEBUG
+EXPO
+EXYNOS7870
+EXYNOS7880
+FASTBOOT_UUU_SUPPORT
+FRED
+FRU_SC
+FSL_ISBC_KEY_EXT
+GENERATE_SMBIOS_TABLE
+GMAC_ROCKCHIP
+I8259_PIC
+IMX_RDC
+INTEL_GENERIC_WIFI
+LOG_SYSLOG
+LS2_SFP
+MALTA
+MEMSIZE_IN_BYTES
+MIPS_BOOT_CMDLINE_LEGACY
+MIPS_BOOT_ENV_LEGACY
+MIPS_BOOT_FDT
+MMC_HW_PARTITIONING
+MMC_VERBOSE
+MSCODE_PARSER
+MUX_MMIO
+NAND_CS_INIT
+NO_FB_CLEAR
+NXP_FSPI
+OFNODE_MULTI_TREE
+PCF8575_GPIO
+PCI_PNP
+PHY_CADENCE_TORRENT
+PHY_J721E_WIZ
+PKCS7_MESSAGE_PARSER
+PKCS7_VERIFY
+PLATDATA
+PRE_CONSOLE_BUFFER
+QFW_PIO
+REGULATOR_RK8XX
+RESTORE_EXCEPTION_VECTOR_BASE
+ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
+SEC_FIRMWARE_ARMV8_PSCI
+SERIAL_PUTS
+SERIAL_RX_BUFFER
+SHA512_HW_ACCEL
+SILENT_CONSOLE_UPDATE_ON_RELOC
+SILENT_CONSOLE_UPDATE_ON_SET
+SIMPLE_BUS_CORRECT_RANGE
+SMC911X_32_BIT
+SPI_DIRMAP
+SPI_FLASH_BAR
+SPI_FLASH_MACRONIX
+SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
+STM32_ETZPC
+SYSRESET_AT91
+SYSRESET_X86
+SYS_DEVICE_NULLDEV
+SYS_WHITE_ON_BLACK
+TARGET_DENEB
+TARGET_EVB_RK3399
+TARGET_GIEDI
+TARGET_KMCOGE5NE
+TARGET_KMETER1
+TARGET_ST_STM32MP15X
+TURRIS_OMNIA_MCU
+USB_GADGET_OS_DESCRIPTORS
+UT_DM
+UT_UNICODE
+X509_CERTIFICATE_PARSER
+XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
+XILINX_MICROBLAZE0_USR_EXCEP
-- 
2.39.1.581.gbfd45094c4-goog