[PATCH] arm: mvebu: Add support for Synology DS116 (Armada 385)
Stefan Roese
sr at denx.de
Mon Feb 13 15:00:38 CET 2023
On 2/9/23 23:00, Tony Dinh wrote:
> Synology DS116 is a NAS based on Marvell Armada 385 SoC.
>
> Board Specification:
>
> - Marvel MV88F6820 Dual Core at 1.8GHz
> - 1 GiB DDR3 RAM
> - 8MB Macronix mx25l6405d SPI flash
> - I2C
> - 2x USB 3.0
> - 1x GBE LAN port (PHY: Marvell 88E1510)
> - 1x SATA (6 Gbps)
> - 3x LED
> - PIC16F1829 (connected to uart1)
> - GPIO fan
> - serial console
>
> Note that this patch depends on the add-support for Thecus N2350 patch:
> https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/
>
> Signed-off-by: Tony Dinh <mibodhi at gmail.com>
Applied to u-boot-marvell/master
Thanks,
Stefan
> ---
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/armada-385-synology-ds116.dts | 291 +++++++++++++++++++++
> arch/arm/mach-mvebu/Kconfig | 7 +
> board/Synology/ds116/MAINTAINERS | 7 +
> board/Synology/ds116/Makefile | 6 +
> board/Synology/ds116/ds116.c | 135 ++++++++++
> configs/ds116_defconfig | 92 +++++++
> include/configs/ds116.h | 56 ++++
> 8 files changed, 595 insertions(+)
> create mode 100644 arch/arm/dts/armada-385-synology-ds116.dts
> create mode 100644 board/Synology/ds116/MAINTAINERS
> create mode 100644 board/Synology/ds116/Makefile
> create mode 100644 board/Synology/ds116/ds116.c
> create mode 100644 configs/ds116_defconfig
> create mode 100644 include/configs/ds116.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index dee298228f..9d647b9639 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -247,6 +247,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
> armada-385-atl-x530.dtb \
> armada-385-atl-x530DP.dtb \
> armada-385-db-88f6820-amc.dtb \
> + armada-385-synology-ds116.dtb \
> armada-385-thecus-n2350.dtb \
> armada-385-turris-omnia.dtb \
> armada-388-clearfog.dtb \
> diff --git a/arch/arm/dts/armada-385-synology-ds116.dts b/arch/arm/dts/armada-385-synology-ds116.dts
> new file mode 100644
> index 0000000000..82a0373f7f
> --- /dev/null
> +++ b/arch/arm/dts/armada-385-synology-ds116.dts
> @@ -0,0 +1,291 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Device Tree file for Synology DS116 NAS
> + *
> + * Copyright (C) 2017 Willy Tarreau <w at 1wt.eu>
> + */
> +
> +/dts-v1/;
> +#include "armada-385.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Synology DS116";
> + compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>; /* 1 GB */
> + };
> +
> + soc {
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
> + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
> + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
> + MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
> +
> + internal-regs {
> + i2c at 11000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + eeprom at 57 {
> + compatible = "atmel,24c64";
> + reg = <0x57>;
> + };
> + };
> +
> + serial at 12000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> + };
> +
> + serial at 12100 {
> + /* A PIC16F1829 is connected to uart1 at 9600 bps,
> + * and takes single-character orders :
> + * "1" : power off // already handled by the poweroff node
> + * "2" : short beep
> + * "3" : long beep
> + * "4" : turn the power LED ON
> + * "5" : flash the power LED
> + * "6" : turn the power LED OFF
> + * "7" : turn the status LED OFF
> + * "8" : turn the status LED ON
> + * "9" : flash the status LED
> + * "A" : flash the motherboard LED (D8)
> + * "B" : turn the motherboard LED OFF
> + * "C" : hard reset
> + */
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "okay";
> + };
> +
> + poweroff at 12100 {
> + compatible = "synology,power-off";
> + reg = <0x12100 0x100>;
> + clocks = <&coreclk 0>;
> + };
> +
> + ethernet at 70000 {
> + pinctrl-names = "default";
> + phy = <&phy0>;
> + phy-mode = "sgmii";
> + buffer-manager = <&bm>;
> + bm,pool-long = <0>;
> + status = "okay";
> + };
> +
> + mdio at 72004 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mdio_pins>;
> +
> + phy0: ethernet-phy at 1 {
> + reg = <1>;
> + };
> + };
> +
> + sata at a8000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sata0_pins>;
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + sata0: sata-port at 0 {
> + reg = <0>;
> + target-supply = <®_5v_sata0>;
> + };
> + };
> +
> + bm at c8000 {
> + status = "okay";
> + };
> +
> + usb3 at f0000 {
> + usb-phy = <&usb3_0_phy>;
> + status = "okay";
> + };
> +
> + usb3 at f8000 {
> + usb-phy = <&usb3_1_phy>;
> + status = "okay";
> + };
> + };
> +
> + bm-bppi {
> + status = "okay";
> + };
> +
> + gpio-fan {
> + compatible = "gpio-fan";
> + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
> + <&gpio1 17 GPIO_ACTIVE_HIGH>,
> + <&gpio1 16 GPIO_ACTIVE_HIGH>;
> + gpio-fan,speed-map = < 0 0
> + 1500 1
> + 2500 2
> + 3000 3
> + 3400 4
> + 3700 5
> + 3900 6
> + 4000 7>;
> + #cooling-cells = <2>;
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> +
> + /* The green part is on gpio0.20 which is also used by
> + * sata0, and accesses to SATA disk 0 make it blink so it
> + * doesn't need to be declared here.
> + */
> + orange {
> + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
> + label = "ds116:orange:disk";
> + default-state = "off";
> + };
> + };
> + };
> +
> + usb3_0_phy: usb3_0_phy {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <®_usb3_0_vbus>;
> + #phy-cells = <0>;
> + };
> +
> + usb3_1_phy: usb3_1_phy {
> + compatible = "usb-nop-xceiv";
> + vcc-supply = <®_usb3_1_vbus>;
> + #phy-cells = <0>;
> + };
> +
> + reg_usb3_0_vbus: usb3-vbus0 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb3-vbus0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&xhci0_vbus_pins>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_usb3_1_vbus: usb3-vbus1 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb3-vbus1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&xhci1_vbus_pins>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_sata0: pwr-sata0 {
> + compatible = "regulator-fixed";
> + regulator-name = "pwr_en_sata0";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + enable-active-high;
> + regulator-boot-on;
> + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_5v_sata0: v5-sata0 {
> + compatible = "regulator-fixed";
> + regulator-name = "v5.0-sata0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <®_sata0>;
> + };
> +
> + reg_12v_sata0: v12-sata0 {
> + compatible = "regulator-fixed";
> + regulator-name = "v12.0-sata0";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + vin-supply = <®_sata0>;
> + };
> +};
> +
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + status = "okay";
> +
> + spi-flash at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "macronix,mx25l6405d", "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <50000000>;
> + m25p,fast-read;
> +
> + /* Note: there is a redboot partition table despite u-boot
> + * being used. The names presented here are the same as those
> + * found in the FIS directory. There is also a small device
> + * tree in the last 64kB of the RedBoot partition which is not
> + * enumerated. The MAC address and the serial number are listed
> + * in the "vendor" partition.
> + */
> + partition at 0 {
> + label = "RedBoot";
> + reg = <0x00000000 0x000f0000>;
> + read-only;
> + };
> +
> + partition at c0000 {
> + label = "zImage";
> + reg = <0x000f0000 0x002d0000>;
> + };
> +
> + partition at 390000 {
> + label = "rd.gz";
> + reg = <0x003c0000 0x00410000>;
> + };
> +
> + partition at 7d0000 {
> + label = "vendor";
> + reg = <0x007d0000 0x00010000>;
> + read-only;
> + };
> +
> + partition at 7e0000 {
> + label = "RedBoot config";
> + reg = <0x007e0000 0x00010000>;
> + read-only;
> + };
> +
> + partition at 7f0000 {
> + label = "FIS directory";
> + reg = <0x007f0000 0x00010000>;
> + read-only;
> + };
> + };
> +};
> +
> +&pinctrl {
> + /* use only one pin for UART1, as mpp20 is used by sata0 */
> + uart1_pins: uart-pins-1 {
> + marvell,pins = "mpp19";
> + marvell,function = "ua1";
> + };
> +
> + xhci0_vbus_pins: xhci0_vbus_pins {
> + marvell,pins = "mpp58";
> + marvell,function = "gpio";
> + };
> + xhci1_vbus_pins: xhci1_vbus_pins {
> + marvell,pins = "mpp59";
> + marvell,function = "gpio";
> + };
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index f829e40945..16c5e72295 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -169,6 +169,10 @@ config TARGET_DB_MV784MP_GP
> select BOARD_ECC_SUPPORT
> select MV78460
>
> +config TARGET_DS116
> + bool "Support Synology DS116"
> + select 88F6820
> +
> config TARGET_DS414
> bool "Support Synology DS414"
> select MV78230
> @@ -263,6 +267,7 @@ config SYS_BOARD
> default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
> default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
> default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
> + default "ds116" if TARGET_DS116
> default "ds414" if TARGET_DS414
> default "maxbcm" if TARGET_MAXBCM
> default "n2350" if TARGET_N2350
> @@ -283,6 +288,7 @@ config SYS_CONFIG_NAME
> default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
> default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
> default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
> + default "ds116" if TARGET_DS116
> default "ds414" if TARGET_DS414
> default "maxbcm" if TARGET_MAXBCM
> default "n2350" if TARGET_N2350
> @@ -307,6 +313,7 @@ config SYS_VENDOR
> default "Marvell" if TARGET_MVEBU_DB_88F7040
> default "solidrun" if TARGET_CLEARFOG
> default "kobol" if TARGET_HELIOS4
> + default "Synology" if TARGET_DS116
> default "Synology" if TARGET_DS414
> default "thecus" if TARGET_N2350
> default "CZ.NIC" if TARGET_TURRIS_OMNIA
> diff --git a/board/Synology/ds116/MAINTAINERS b/board/Synology/ds116/MAINTAINERS
> new file mode 100644
> index 0000000000..a5080b0d14
> --- /dev/null
> +++ b/board/Synology/ds116/MAINTAINERS
> @@ -0,0 +1,7 @@
> +DS116 BOARD
> +M: Tony Dinh <mibodhi at gmail.com>
> +S: Maintained
> +F: arch/arm/dts/armada-385-synology-ds116.dts
> +F: board/Synology/ds116/
> +F: include/configs/ds116.h
> +F: configs/ds116_defconfig
> diff --git a/board/Synology/ds116/Makefile b/board/Synology/ds116/Makefile
> new file mode 100644
> index 0000000000..952cc1b9da
> --- /dev/null
> +++ b/board/Synology/ds116/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2023 Tony Dinh <mibodhi at gmail.com>
> +#
> +
> +obj-y := ds116.o
> diff --git a/board/Synology/ds116/ds116.c b/board/Synology/ds116/ds116.c
> new file mode 100644
> index 0000000000..cf2575b562
> --- /dev/null
> +++ b/board/Synology/ds116/ds116.c
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023 Tony Dinh <mibodhi at gmail.com>
> + *
> + */
> +
> +#include <i2c.h>
> +#include <init.h>
> +#include <miiphy.h>
> +#include <net.h>
> +#include <netdev.h>
> +#include <asm/global_data.h>
> +#include <asm/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/soc.h>
> +#include <linux/bitops.h>
> +
> +#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
> +#include <../serdes/a38x/high_speed_env_spec.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Those DS116_GPP_xx values and defines in board_serdes_map, and board_topology_map
> + * are taken from Marvell U-Boot version
> + * U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
> + */
> +#define DS116_GPP_OUT_ENA_LOW \
> + (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
> + BIT(10) | BIT(11) | BIT(15) | BIT(19) | BIT(22) | BIT(23) | \
> + BIT(25) | BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
> +#define DS116_GPP_OUT_ENA_MID \
> + (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
> + BIT(16) | BIT(17) | BIT(18) | BIT(26) | BIT(27)))
> +
> +#define DS116_GPP_OUT_VAL_LOW BIT(15)
> +#define DS116_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
> +#define DS116_GPP_POL_LOW 0x0
> +#define DS116_GPP_POL_MID 0x0
> +
> +static struct serdes_map board_serdes_map[] = {
> + {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
> +};
> +
> +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
> +{
> + *serdes_map_array = board_serdes_map;
> + *count = ARRAY_SIZE(board_serdes_map);
> + return 0;
> +}
> +
> +/*
> + * Define the DDR layout / topology here in the board file. This will
> + * be used by the DDR3 init code in the SPL U-Boot version to configure
> + * the DDR3 controller.
> + */
> +static struct mv_ddr_topology_map board_topology_map = {
> + DEBUG_LEVEL_ERROR,
> + 0x1, /* active interfaces */
> + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
> + { { { {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0},
> + {0x1, 0, 0, 0} },
> + SPEED_BIN_DDR_1866L, /* speed_bin */
> + MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
> + MV_DDR_DIE_CAP_4GBIT, /* mem_size - DS116 board has 2x512MB DRAM banks */
> + MV_DDR_FREQ_800, /* frequency */
> + 0, 0, /* cas_wl cas_l */
> + MV_DDR_TEMP_LOW, /* temperature */
> + MV_DDR_TIM_DEFAULT} }, /* timing */
> + BUS_MASK_32BIT, /* Busses mask */
> + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> + NOT_COMBINED, /* ddr twin-die combined */
> + { {0} }, /* raw spd data */
> + {0} /* timing parameters */
> +};
> +
> +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
> +{
> + /* Return the board topology as defined in the board code */
> + return &board_topology_map;
> +}
> +
> +int board_early_init_f(void)
> +{
> + /*
> + * Those MPP values are taken from the Marvell U-Boot version
> + * U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
> + */
> +
> + /* Configure MPP */
> + writel(0x00111111, MVEBU_MPP_BASE + 0x00);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x04);
> + writel(0x11040330, MVEBU_MPP_BASE + 0x08);
> + writel(0x00000011, MVEBU_MPP_BASE + 0x0c);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x10);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x14);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x18);
> + writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
> +
> + /* Set GPP Out value */
> + writel(DS116_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
> + writel(DS116_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
> +
> + /* Set GPP Polarity */
> + writel(DS116_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
> + writel(DS116_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
> +
> + /* Set GPP Out Enable */
> + writel(DS116_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
> + writel(DS116_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> +
> + return 0;
> +}
> +
> +int board_eth_init(struct bd_info *bis)
> +{
> + cpu_eth_init(bis); /* Built in controller(s) come first */
> + return pci_eth_init(bis);
> +}
> diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
> new file mode 100644
> index 0000000000..5546017c58
> --- /dev/null
> +++ b/configs/ds116_defconfig
> @@ -0,0 +1,92 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_CPU_INIT=y
> +CONFIG_SYS_THUMB_BUILD=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SUPPORT_PASSING_ATAGS=y
> +CONFIG_CMDLINE_TAG=y
> +CONFIG_INITRD_TAG=y
> +CONFIG_TEXT_BASE=0x00800000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=2
> +CONFIG_TARGET_DS116=y
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x7E0000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116"
> +CONFIG_SPL_TEXT_BASE=0x40000030
> +CONFIG_SYS_PROMPT="DS116> "
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0xf1012000
> +CONFIG_DEBUG_UART_CLOCK=250000000
> +CONFIG_IDENT_STRING="\nSynology DS116"
> +CONFIG_SYS_LOAD_ADDR=0x800000
> +CONFIG_DEBUG_UART=y
> +CONFIG_AHCI=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
> +CONFIG_BOOTDELAY=10
> +CONFIG_USE_PREBOOT=y
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_MAX_SIZE=0x22fd0
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x40023000
> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK=0x4002c000
> +CONFIG_SPL_I2C=y
> +CONFIG_SYS_MAXARGS=32
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPIO_READ=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_TFTPPUT=y
> +CONFIG_CMD_SNTP=y
> +CONFIG_CMD_DNS=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)"
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_VERSION_VARIABLE=y
> +CONFIG_ARP_TIMEOUT=200
> +CONFIG_NET_RETRY_COUNT=50
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_NETCONSOLE=y
> +CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_AHCI_MVEBU=y
> +CONFIG_LBA48=y
> +CONFIG_SYS_64BIT_LBA=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +CONFIG_MTD=y
> +CONFIG_SF_DEFAULT_SPEED=50000000
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_PHY_MARVELL=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_MVNETA=y
> +CONFIG_MII=y
> +CONFIG_MVMDIO=y
> +CONFIG_PCI=y
> +CONFIG_PCI_MVEBU=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ARMADA_38X=y
> +CONFIG_DM_RTC=y
> +CONFIG_RTC_ARMADA38X=y
> +CONFIG_SCSI=y
> +CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550=y
> +CONFIG_KIRKWOOD_SPI=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> diff --git a/include/configs/ds116.h b/include/configs/ds116.h
> new file mode 100644
> index 0000000000..031f4f6afc
> --- /dev/null
> +++ b/include/configs/ds116.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2023 Tony Dinh <mibodhi at gmail.com>
> + *
> + */
> +
> +#ifndef _CONFIG_DS116_H
> +#define _CONFIG_DS116_H
> +
> +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
> +
> +/* Keep device tree and initrd in lower memory so the kernel can access them */
> +#define RELOCATION_LIMITS_ENV_SETTINGS \
> + "fdt_high=0x10000000\0" \
> + "initrd_high=0x10000000\0"
> +
> +/*
> + * mv-common.h should be defined after CMD configs since it used them
> + * to enable certain macros
> + */
> +#include "mv-common.h"
> +
> +/* Include the common distro boot environment */
> +#ifndef CONFIG_SPL_BUILD
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(USB, usb, 0) \
> + func(SCSI, scsi, 0) \
> + func(PXE, pxe, na) \
> + func(DHCP, dhcp, na)
> +
> +#define KERNEL_ADDR_R __stringify(0x1000000)
> +#define FDT_ADDR_R __stringify(0x2000000)
> +#define RAMDISK_ADDR_R __stringify(0x2200000)
> +#define SCRIPT_ADDR_R __stringify(0x1800000)
> +#define PXEFILE_ADDR_R __stringify(0x1900000)
> +
> +#define LOAD_ADDRESS_ENV_SETTINGS \
> + "kernel_addr_r=" KERNEL_ADDR_R "\0" \
> + "fdt_addr_r=" FDT_ADDR_R "\0" \
> + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
> + "scriptaddr=" SCRIPT_ADDR_R "\0" \
> + "pxefile_addr_r=" PXEFILE_ADDR_R "\0"
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + RELOCATION_LIMITS_ENV_SETTINGS \
> + LOAD_ADDRESS_ENV_SETTINGS \
> + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> + "console=ttyS0,115200\0" \
> + BOOTENV
> +
> +#endif /* CONFIG_SPL_BUILD */
> +
> +#endif /* _CONFIG_DS116_H */
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
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