[PATCH v1 1/1] fpga: zynqmppl: fix fpga loads command for unencrypted use case

[Soma, Ashok Reddy]

Acked-by: Ashok Reddy Soma <ashok.reddy.soma at amd.com> 

Thanks,
Ashok

> -----Original Message-----
> From: Neal Frager <neal.frager at amd.com>
> Sent: Tuesday, February 14, 2023 6:50 PM
> To: u-boot at lists.denx.de; git-dev (AMD-Xilinx) <git-dev at amd.com>
> Cc: Simek, Michal <michal.simek at amd.com>; Soma, Ashok Reddy
> <ashok.reddy.soma at amd.com>; Manne, Nava kishore
> <nava.kishore.manne at amd.com>; Erkiaga Elorza, Ibai <ibai.erkiaga-
> elorza at amd.com>; Frager, Neal <neal.frager at amd.com>
> Subject: [PATCH v1 1/1] fpga: zynqmppl: fix fpga loads command for
> unencrypted use case
> 
> When using the fpga loads command, the driver is passing the AES
> encryption key address is all cases.  However, for the authenticated, but not
> encrypted use case, there is no AES encryption key, and this value is 0.
> 
> When AES encryption is not used on the fpga bitstream, the pmufw assumes
> that the AES key address is a bitstream size value like what is used by the
> unsecure fpga load command.
> 
> To fix the problem, this patch checks to see if the AES key address is zero.
> If the AES key address is zero, it means that AES is not being used on the
> bitstream and the bitstream size should be passed instead.  Thus, matching
> the fpga load functionality.
> 
> Signed-off-by: Neal Frager <neal.frager at amd.com>
> ---
>  drivers/fpga/zynqmppl.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index
> 6b394869db..718c04b22c 100644
> --- a/drivers/fpga/zynqmppl.c
> +++ b/drivers/fpga/zynqmppl.c
> @@ -278,10 +278,16 @@ static int zynqmp_loads(xilinx_desc *desc, const
> void *buf, size_t bsize,
>  	buf_lo = lower_32_bits((ulong)buf);
>  	buf_hi = upper_32_bits((ulong)buf);
> 
> -	ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
> +	if ((u32)(uintptr_t)fpga_sec_info->userkey_addr)
> +		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
>  				buf_hi,
> -			 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
> -			 flag, ret_payload);
> +				(u32)(uintptr_t)fpga_sec_info-
> >userkey_addr,
> +				flag, ret_payload);
> +	else
> +		ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
> +					buf_hi, (u32)bsize,
> +					flag, ret_payload);
> +
>  	if (ret)
>  		puts("PL FPGA LOAD fail\n");
>  	else
> --
> 2.17.1