[PATCH v3 01/14] clk: imx8mp: Add EQoS MAC clock

[Peng Fan]

On 2/12/2023 5:47 AM, Marek Vasut wrote:
> Add clock for the DWMAC EQoS block. This is used among other things
> to configure the MII clock via DM CLK.
> 
> Acked-by: Sean Anderson <seanga2 at gmail.com>
> Signed-off-by: Marek Vasut <marex at denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro at collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin at leica-geosystems.com>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Joe Hershberger <joe.hershberger at ni.com>
> Cc: Lukasz Majewski <lukma at denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler at toradex.com>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Michael Trimarchi <michael at amarulasolutions.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> Cc: Sean Anderson <seanga2 at gmail.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Tim Harvey <tharvey at gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai at amarulasolutions.com>
> Cc: u-boot at lists.denx.de

Reviewed-by: Peng Fan <peng.fan at nxp.com>

> ---
> V2: Add AB from Sean
> V3: No change
> ---
>   drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index ffbc1d1ba9f..6dda0403e35 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>   					 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
>   					 "audio_pll2_out", "sys_pll1_133m", };
>   
> +static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
> +					     "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
> +					     "video_pll1_out", "clk_ext4", };
> +
> +static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
> +						   "clk_ext1", "clk_ext2", "clk_ext3",
> +						   "clk_ext4", "video_pll1_out", };
> +
>   static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
>   					   "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
>   					   "audio_pll2_out", "sys_pll1_100m", };
> @@ -250,6 +258,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
>   	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
>   	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
> +	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
>   	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
>   	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
>   	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
> @@ -292,10 +302,13 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
>   	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
>   	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
>   	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>   	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
>   	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
>   	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
>   	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
>   	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
>   	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));