[RFC PATCH v3] doc: arch: Add document for RISC-V architecture

[Rick Chen]

> From: Peter Yu-Chien Lin(林宇謙) <peterlin at andestech.com>
> Sent: Tuesday, February 14, 2023 6:19 PM
> To: u-boot at lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; sjg at chromium.org; xypron.glpk at gmx.de; Peter Yu-Chien Lin(林宇謙) <peterlin at andestech.com>; Samuel Holland <samuel at sholland.org>
> Subject: [RFC PATCH v3] doc: arch: Add document for RISC-V architecture
>
> This patch adds a brief introduction to the RISC-V architecture and the typical boot process used on a variety of RISC-V platforms.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Samuel Holland <samuel at sholland.org>
> Reviewed-by: Simon Glass <sjg at chromium.org>
> ---
> Changes v1 -> v2
> - Use 'boot phases' rather than 'boot stages'
> - Pick up Samuel and Simon's RB tags
> Changes v2 -> v3
> - Follow the suggestion by Heinrich [1]
> - Add the document as an entry of Andes maintainer in MAINTAINERS
> - Add some pointers to OpenSBI document
>
> [1] https://patchwork.ozlabs.org/project/uboot/patch/20230212070053.14800-1-peterlin@andestech.com/
> ---
>  MAINTAINERS        |  1 +
>  doc/arch/index.rst |  1 +
>  doc/arch/riscv.rst | 74 ++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 76 insertions(+)
>  create mode 100644 doc/arch/riscv.rst

Reviewed-by: Rick Chen <rick at andestech.com>