[PATCH 0/2] Keep PLL power on

Dylan Hung dylan_hung at aspeedtech.com
Tue Feb 21 14:01:08 CET 2023


There are several PLLs in AST2600 that provide clock sources for various
hardware blocks. According to the PLL vendor, the setting sequence was
incorrect, since the PLL power should kept on during initialization.
This patch series fixes the PLL setting sequence, including the MPLL in
the DRAM driver and the others in the clock driver.

Dylan Hung (2):
  ram: ast2600: Keep MPLL power on
  clk: ast2600: Keep PLL power on

 drivers/clk/aspeed/clk_ast2600.c   | 3 +--
 drivers/ram/aspeed/sdram_ast2600.c | 6 +++---
 2 files changed, 4 insertions(+), 5 deletions(-)

-- 
2.25.1



More information about the U-Boot mailing list