[RFC PATCH v3 7/9] ARM: rzn1: basic support for Renesas RZ/N1 SoC

[Ralph Siemsen]

The RZ/N1 is a family of SoC devics from Renesas, featuring:

* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD

Add basic support in the form of ARCH_RZN1 symbol.

Signed-off-by: Ralph Siemsen <ralph.siemsen at linaro.org>
---

(no changes since v1)

 arch/arm/Kconfig              | 17 +++++++++++++++++
 arch/arm/Makefile             |  1 +
 arch/arm/mach-rzn1/Kconfig    | 18 ++++++++++++++++++
 arch/arm/mach-rzn1/Makefile   |  3 +++
 arch/arm/mach-rzn1/cpu_info.c | 19 +++++++++++++++++++
 5 files changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-rzn1/Kconfig
 create mode 100644 arch/arm/mach-rzn1/Makefile
 create mode 100644 arch/arm/mach-rzn1/cpu_info.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd7fffcce0..8e2a30f852 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
 	imply SYS_THUMB_BUILD
 	imply ARCH_MISC_INIT if DISPLAY_CPUINFO
 
+config ARCH_RZN1
+	bool "Reneasa RZ/N1 SoC"
+	select CLK
+	select CLK_RENESAS
+	select CLK_R9A06G032
+	select DM
+	select DM_ETH
+	select DM_SERIAL
+	select PINCTRL
+	select PINCONF
+	select REGMAP
+	select SYSRESET
+	select SYSRESET_SYSCON
+	imply CMD_DM
+
 config ARCH_SNAPDRAGON
 	bool "Qualcomm Snapdragon SoCs"
 	select ARM64
@@ -2207,6 +2222,8 @@ source "arch/arm/mach-owl/Kconfig"
 
 source "arch/arm/mach-rmobile/Kconfig"
 
+source "arch/arm/mach-rzn1/Kconfig"
+
 source "arch/arm/mach-meson/Kconfig"
 
 source "arch/arm/mach-mediatek/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ac602aed9c..1ec95a87e1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -76,6 +76,7 @@ machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
 machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
+machine-$(CONFIG_ARCH_RZN1)		+= rzn1
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
diff --git a/arch/arm/mach-rzn1/Kconfig b/arch/arm/mach-rzn1/Kconfig
new file mode 100644
index 0000000000..707895874d
--- /dev/null
+++ b/arch/arm/mach-rzn1/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_RZN1
+
+choice
+	prompt "Target Renesas RZ/N1 SoC select"
+	default RZN1
+
+config RZN1
+	bool "Renesas ARM SoCs RZ/N1 (32bit)"
+	select CPU_V7A
+	select ARMV7_SET_CORTEX_SMPEN if !SPL
+	select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+
+endchoice
+
+config SYS_SOC
+	default "rzn1"
+
+endif
diff --git a/arch/arm/mach-rzn1/Makefile b/arch/arm/mach-rzn1/Makefile
new file mode 100644
index 0000000000..b20f845c0f
--- /dev/null
+++ b/arch/arm/mach-rzn1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y = cpu_info.o
diff --git a/arch/arm/mach-rzn1/cpu_info.c b/arch/arm/mach-rzn1/cpu_info.c
new file mode 100644
index 0000000000..37c2492b51
--- /dev/null
+++ b/arch/arm/mach-rzn1/cpu_info.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+	dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	printf("CPU: Renesas Electronics RZ/N1\n");
+	return 0;
+}
+#endif
-- 
2.25.1