[PATCH 1/2] clk: sunxi: add THS clk/reset

[Andre Przywara]

On Mon, 13 Feb 2023 10:42:55 +0800
qianfanguijin at 163.com wrote:

Hi,

> From: qianfan Zhao <qianfanguijin at 163.com>
> 
> Add clock/reset definitions for THS peripherals.

the bits look alright, compared against the manual. But it misses the
A64 clocks, the THS driver would cover that SoC, too.

Cheers,
Andre

> Signed-off-by: qianfan Zhao <qianfanguijin at 163.com>
> ---
>  drivers/clk/sunxi/clk_h3.c  | 5 +++++
>  drivers/clk/sunxi/clk_h6.c  | 4 ++++
>  drivers/clk/sunxi/clk_r40.c | 5 +++++
>  3 files changed, 14 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
> index 213ab510ed..774d67cbfa 100644
> --- a/drivers/clk/sunxi/clk_h3.c
> +++ b/drivers/clk/sunxi/clk_h3.c
> @@ -38,6 +38,7 @@ static struct ccu_clk_gate h3_gates[] = {
>  	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
>  
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
> +	[CLK_BUS_THS]		= GATE(0x068, BIT(8)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
>  	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
> @@ -49,6 +50,8 @@ static struct ccu_clk_gate h3_gates[] = {
>  
>  	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
>  
> +	[CLK_THS]		= GATE(0x074, BIT(31)),
> +
>  	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
>  	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
>  
> @@ -98,6 +101,8 @@ static struct ccu_reset h3_resets[] = {
>  
>  	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
>  
> +	[RST_BUS_THS]		= RESET(0x2d0, BIT(8)),
> +
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
>  	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index 24eb9725db..5464530056 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -42,6 +42,8 @@ static struct ccu_clk_gate h6_gates[] = {
>  
>  	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
>  
> +	[CLK_BUS_THS]		= GATE(0x9fc, BIT(0)),
> +
>  	[CLK_USB_PHY0]		= GATE(0xa70, BIT(29)),
>  	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
>  
> @@ -91,6 +93,8 @@ static struct ccu_reset h6_resets[] = {
>  
>  	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
>  
> +	[RST_BUS_THS]		= RESET(0x9fc, BIT(16)),
> +
>  	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
>  
>  	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
> index 630e80d2b4..4fbfd28207 100644
> --- a/drivers/clk/sunxi/clk_r40.c
> +++ b/drivers/clk/sunxi/clk_r40.c
> @@ -42,6 +42,7 @@ static struct ccu_clk_gate r40_gates[] = {
>  	[CLK_BUS_TCON_TOP]	= GATE(0x064, BIT(30)),
>  
>  	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
> +	[CLK_BUS_THS]		= GATE(0x068, BIT(8)),
>  
>  	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
>  	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
> @@ -57,6 +58,8 @@ static struct ccu_clk_gate r40_gates[] = {
>  	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
>  	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
>  
> +	[CLK_THS]		= GATE(0x074, BIT(31)),
> +
>  	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
>  	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
>  	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
> @@ -113,6 +116,8 @@ static struct ccu_reset r40_resets[] = {
>  	[RST_BUS_TCON_TV1]	= RESET(0x2c4, BIT(29)),
>  	[RST_BUS_TCON_TOP]	= RESET(0x2c4, BIT(30)),
>  
> +	[RST_BUS_THS]		= RESET(0x2d0, BIT(8)),
> +
>  	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
>  	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
>  	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),