[PATCH] Reads high bits of DDR type for Rockchip

[Recursive G]

Hi Jonas,

Thank you for the reply and your patch does work.
How do I mark mine as retracted?

Best,
R.

Jonas Karlman <jonas at kwiboo.se> 于2023年2月26日周日 09:00写道：
>
> Hi,
>
> Please try the series at [1], it should solve the same issue you are
> trying to solve with this patch. That series is also queued in the
> rockchip U-Boot Custodian Tree.
>
> [1] https://patchwork.ozlabs.org/project/uboot/cover/20230207172707.4094859-1-jonas@kwiboo.se/
>
> Regards,
> Jonas
>
> On 2023-02-25 20:15, Recursive G wrote:
> > Bit layout decipered from
> > https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b>> Tested on a rk3568 device.
> >
> > Signed-off-by: Recursive G <g.recursive at gmail.com>
> > ---
> >  arch/arm/include/asm/arch-rockchip/sdram.h | 3 +++
> >  arch/arm/mach-rockchip/sdram.c             | 1 +
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h
> > b/arch/arm/include/asm/arch-rockchip/sdram.h
> > index cf2a7b7d10..dec83420bc 100644
> > --- a/arch/arm/include/asm/arch-rockchip/sdram.h
> > +++ b/arch/arm/include/asm/arch-rockchip/sdram.h
> > @@ -61,6 +61,7 @@ enum {
> >
> >  /*
> >   * sys_reg3 bitfield struct
> > + * [13:12] high bits of ddrtype
> >   * [7] high bit of cs0_row_ch1
> >   * [6] high bit of cs1_row_ch1
> >   * [5] high bit of cs0_row_ch0
> > @@ -76,6 +77,8 @@ enum {
> >  #define SYS_REG_EXTEND_CS1_ROW_MASK 1
> >  #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
> >  #define SYS_REG_CS1_COL_MASK 3
> > +#define SYS_REG_DDRTYPE_HI_SHIFT 9
> > +#define SYS_REG_DDRTYPE_HI_MASK 0x18
> >
> >  /* Get sdram size decode from reg */
> >  size_t rockchip_sdram_size(phys_addr_t reg);
> > diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> > index e086c47f3c..60ef48eb67 100644
> > --- a/arch/arm/mach-rockchip/sdram.c
> > +++ b/arch/arm/mach-rockchip/sdram.c
> > @@ -90,6 +90,7 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> >          & SYS_REG_NUM_CH_MASK);
> >
> >   dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
> > + dram_type |= (sys_reg3 >> SYS_REG_DDRTYPE_HI_SHIFT) & SYS_REG_DDRTYPE_HI_MASK;
> >   debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
> >   for (ch = 0; ch < ch_num; ch++) {
> >   rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
>