[PATCH v2] riscv: ax25: bypass malloc when spl fit boots from ram

[Rick Chen]

> Hi Rick,
>
> On 1/3/23 02:20, Rick Chen wrote:
> > When fit image boots from ram, the payload will
> > be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> > In spl fit generic flow, it will malloc another
> > memory address and copy whole fit image to this
> > malloc address.  But it is un-necessary for booting
> > from RAM.
> >
> > This patch improves this flow by declare the
> > board_spl_fit_buffer_addr() to replace the original one.
> > The larger image size (eq: Kernel Image 10~20MB), it
> > can save more booting time.
> >
> > Also enhance memcpy function by checking source and
> > destination address. If they are the same address,
> > just return and don't copy data anymore.
>
> Starting a paragraph with "also" is a good indication that this should
> be split into two separate patches.

OK, I will separate it to another patch.

>
> > Signed-off-by: Rick Chen <rick at andestech.com>
> > ---
> > Changes in v2
> >  - Move spl.c to board level instead of arch level
> > ---
> >  arch/riscv/cpu/ax25/Makefile |  1 +
> >  arch/riscv/cpu/ax25/spl.c    | 31 +++++++++++++++++++++++++++++++
> >  arch/riscv/lib/memcpy.S      |  2 ++
> >  3 files changed, 34 insertions(+)
> >  create mode 100644 arch/riscv/cpu/ax25/spl.c
> >
> > diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
> > index 318baccb09..f1c21eadd4 100644
> > --- a/arch/riscv/cpu/ax25/Makefile
> > +++ b/arch/riscv/cpu/ax25/Makefile
> > @@ -5,3 +5,4 @@
> >
> >  obj-y        := cpu.o
> >  obj-y        += cache.o
> > +obj-y += spl.o
>
> nit: alignment

OK, I will fix it.

>
> > diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c
> > new file mode 100644
> > index 0000000000..6bf357d26d
> > --- /dev/null
> > +++ b/arch/riscv/cpu/ax25/spl.c
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2023 Andes Technology Corporation
> > + * Rick Chen, Andes Technology Corporation <rick at andestech.com>
> > + */
> > +#include <common.h>
> > +#include <cpu_func.h>
> > +#include <hang.h>
> > +#include <init.h>
> > +#include <log.h>
> > +#include <spl.h>
> > +#include <asm/global_data.h>
> > +#include <asm/system.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#if CONFIG_IS_ENABLED(RAM_SUPPORT)
> > +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
> > +{
> > +     return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset);
> > +}
> > +
> > +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
> > +{
> > +     void *buf;
> > +
> > +     buf = spl_get_load_buffer(0, sectors * bl_len);
> > +
> > +     return buf;
>
> nit: this could all be one line

OK, I will refine it.

B,R,
Rick

>
> Regards,
> Samuel
>
> > +}
> > +#endif
> > diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
> > index 00672c19ad..9884077c93 100644
> > --- a/arch/riscv/lib/memcpy.S
> > +++ b/arch/riscv/lib/memcpy.S
> > @@ -9,6 +9,7 @@
> >  /* void *memcpy(void *, const void *, size_t) */
> >  ENTRY(__memcpy)
> >  WEAK(memcpy)
> > +     beq     a0, a1, .copy_end
> >       /* Save for return value */
> >       mv      t6, a0
> >
> > @@ -121,6 +122,7 @@ WEAK(memcpy)
> >  2:
> >
> >       mv      a0, t6
> > +.copy_end:
> >       ret
> >
> >  .Lmisaligned_word_copy:
>