[PATCH 18/19] global: Finish CONFIG -> CFG migration
Tom Rini
trini at konsulko.com
Tue Jan 10 17:19:45 CET 2023
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <trini at konsulko.com>
---
README | 24 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 166 +++++-----
.../arm/include/asm/arch-fsl-layerscape/cpu.h | 96 +++---
.../include/asm/arch-rockchip/ddr_rk3288.h | 2 +-
.../include/asm/arch-rockchip/sdram_rk322x.h | 2 +-
arch/arm/include/asm/arch-sunxi/i2c.h | 2 +-
arch/arm/mach-omap2/fdt-common.c | 4 +-
arch/arm/mach-omap2/omap5/fdt.c | 8 +-
.../arm/mach-rmobile/include/mach/rcar-mstp.h | 96 +++---
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
arch/arm/mach-tegra/tegra20/warmboot_avp.c | 2 +-
arch/arm/mach-tegra/tegra20/warmboot_avp.h | 4 +-
arch/m68k/cpu/mcf523x/interrupts.c | 8 +-
arch/m68k/cpu/mcf52x2/interrupts.c | 14 +-
arch/m68k/cpu/mcf530x/interrupts.c | 2 +-
arch/m68k/cpu/mcf532x/interrupts.c | 8 +-
arch/m68k/cpu/mcf5445x/interrupts.c | 8 +-
arch/m68k/include/asm/cache.h | 42 +--
arch/m68k/include/asm/coldfire/intctrl.h | 8 +-
arch/m68k/include/asm/immap.h | 290 +++++++++---------
arch/m68k/lib/cache.c | 28 +-
arch/m68k/lib/interrupts.c | 2 +-
arch/m68k/lib/time.c | 24 +-
arch/mips/mach-mtmips/mt7621/spl/start.S | 8 +-
arch/powerpc/cpu/mpc83xx/bats/bats.h | 128 ++++----
arch/powerpc/cpu/mpc83xx/cpu_init.c | 26 +-
arch/powerpc/cpu/mpc83xx/hid/hid.h | 12 +-
arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h | 4 +-
arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h | 32 +-
arch/powerpc/cpu/mpc83xx/spd_sdram.c | 6 +-
arch/powerpc/cpu/mpc83xx/spl_minimal.c | 10 +-
arch/powerpc/cpu/mpc83xx/start.S | 154 +++++-----
arch/powerpc/cpu/mpc85xx/cpu_init.c | 56 ++--
arch/powerpc/cpu/mpc85xx/fdt.c | 10 +-
arch/powerpc/cpu/mpc85xx/liodn.c | 6 +-
arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 16 +-
arch/powerpc/include/asm/fsl_pamu.h | 2 +-
arch/powerpc/include/asm/fsl_secure_boot.h | 8 +-
arch/powerpc/lib/bootm.c | 6 +-
arch/powerpc/lib/interrupts.c | 6 +-
arch/riscv/include/asm/encoding.h | 2 +-
arch/x86/include/asm/acpi/chromeos.asl | 4 +-
board/alliedtelesis/x530/x530.c | 6 +-
board/armltd/vexpress64/vexpress64.c | 2 +-
.../compulab/imx8mm-cl-iot-gate/eeprom_spl.c | 6 +-
board/davinci/da8xxevm/da850evm.c | 6 +-
board/davinci/da8xxevm/omapl138_lcdk.c | 4 +-
board/eets/pdu001/board.c | 4 +-
board/freescale/common/cadmus.c | 12 +-
board/freescale/common/fsl_chain_of_trust.c | 6 +-
board/freescale/common/pixis.c | 30 +-
board/freescale/ls1043aqds/eth.c | 4 +-
board/freescale/ls1043ardb/eth.c | 4 +-
board/freescale/ls1046afrwy/eth.c | 2 +-
board/freescale/ls1046aqds/eth.c | 2 +-
board/freescale/ls1046ardb/eth.c | 4 +-
board/freescale/p2041rdb/eth.c | 4 +-
board/freescale/t102xrdb/eth_t102xrdb.c | 4 +-
board/freescale/t104xrdb/eth.c | 2 +-
board/freescale/t208xqds/eth_t208xqds.c | 4 +-
board/freescale/t4rdb/eth.c | 4 +-
board/logicpd/omap3som/omap3logic.c | 4 +-
board/renesas/blanche/blanche.c | 2 +-
board/sysam/amcore/amcore.c | 2 +-
board/ti/evm/evm.c | 4 +-
cmd/ximg.c | 6 +-
common/command.c | 2 +-
doc/README.davinci | 2 +-
doc/README.fec_mxc | 2 +-
doc/develop/environment.rst | 2 +-
doc/usage/netconsole.rst | 2 +-
drivers/crypto/fsl/jr.c | 6 +-
drivers/crypto/fsl/jr.h | 2 +-
drivers/ddr/fsl/ctrl_regs.c | 10 +-
drivers/ddr/fsl/options.c | 6 +-
drivers/fpga/virtex2.c | 8 +-
drivers/fpga/zynqpl.c | 6 +-
drivers/gpio/mpc83xx_gpio.c | 40 +--
drivers/i2c/fsl_i2c.c | 16 +-
drivers/i2c/lpc32xx_i2c.c | 16 +-
drivers/i2c/mvtwsi.c | 6 +-
drivers/i2c/octeon_i2c.c | 4 +-
drivers/misc/gpio_led.c | 6 +-
drivers/mtd/nand/raw/kmeter1_nand.c | 12 +-
drivers/mtd/spi/fsl_espi_spl.c | 4 +-
drivers/net/ag7xxx.c | 30 +-
drivers/net/designware.c | 18 +-
drivers/net/designware.h | 18 +-
drivers/net/eepro100.c | 24 +-
drivers/net/fec_mxc.c | 8 +-
drivers/net/fm/fm.c | 2 +-
drivers/net/mcfmii.c | 12 +-
drivers/net/mt7628-eth.c | 12 +-
drivers/net/mvpp2.c | 2 +-
drivers/net/netconsole.c | 6 +-
drivers/net/npcm750_eth.c | 32 +-
drivers/net/octeon/octeon_eth.c | 6 +-
drivers/net/qe/dm_qe_uec.c | 8 +-
drivers/net/sun8i_emac.c | 38 +--
drivers/net/ti/davinci_emac.c | 20 +-
drivers/phy/phy-ti-am654.c | 8 +-
drivers/pinctrl/nxp/pinctrl-imx.h | 2 +-
drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 4 +-
drivers/pinctrl/nxp/pinctrl-imx8ulp.c | 4 +-
drivers/pinctrl/nxp/pinctrl-mxs.c | 6 +-
drivers/pinctrl/nxp/pinctrl-mxs.h | 6 +-
drivers/pinctrl/pinctrl-zynqmp.c | 8 +-
drivers/qe/qe.c | 4 +-
drivers/ram/aspeed/sdram_ast2600.c | 12 +-
drivers/ram/octeon/octeon_ddr.c | 8 +-
drivers/ram/rockchip/dmc-rk3368.c | 2 +-
drivers/serial/ns16550.c | 12 +-
drivers/serial/serial_omap.c | 6 +-
drivers/serial/usbtty.c | 28 +-
drivers/serial/usbtty.h | 18 +-
drivers/spi/mxc_spi.c | 6 +-
drivers/timer/mpc83xx_timer.c | 6 +-
drivers/ufs/ufs.h | 2 +-
drivers/usb/gadget/ci_udc.c | 10 +-
drivers/usb/gadget/ci_udc.h | 6 +-
drivers/usb/host/ehci-faraday.c | 6 +-
drivers/usb/host/ehci-tegra.c | 6 +-
drivers/usb/musb-new/linux-compat.h | 4 +-
drivers/usb/musb-new/musb_core.c | 4 +-
drivers/usb/musb-new/musb_core.h | 2 +-
drivers/usb/ulpi/omap-ulpi-viewport.c | 2 +-
drivers/usb/ulpi/ulpi-viewport.c | 2 +-
drivers/usb/ulpi/ulpi.c | 2 +-
include/command.h | 4 +-
include/env_callback.h | 6 +-
include/fm_eth.h | 28 +-
include/fsl_ddr_sdram.h | 16 +-
include/fsl_usb.h | 42 +--
include/usb/ulpi.h | 4 +-
lib/gzip.c | 14 +-
lib/time.c | 6 +-
net/bootp.c | 14 +-
137 files changed, 1087 insertions(+), 1087 deletions(-)
diff --git a/README b/README
index fe571f7ef0a6..40619ee40c54 100644
--- a/README
+++ b/README
@@ -445,12 +445,12 @@ The following options need to be configured:
example "env grep" and "setexpr".
- Watchdog:
- CONFIG_SYS_WATCHDOG_FREQ
+ CFG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
- CONFIG_SYS_WATCHDOG_FREQ interrupts. If not set by the
+ CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the
board configuration file, a default of CONFIG_SYS_HZ/2
- (i.e. 500) is used. Setting CONFIG_SYS_WATCHDOG_FREQ
+ (i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ
to 0 disables calling WATCHDOG_RESET() from the timer
interrupt.
@@ -523,7 +523,7 @@ The following options need to be configured:
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
+ CFG_SYS_DAVINCI_EMAC_PHY_COUNT
Define this if you have more then 3 PHYs.
CONFIG_FTGMAC100
@@ -653,7 +653,7 @@ The following options need to be configured:
To enable the ULPI layer support, define CONFIG_USB_ULPI and
CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
If your ULPI phy needs a different reference clock than the
- standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
+ standard 24 MHz then you have to define CFG_ULPI_REF_CLK to
the appropriate value in Hz.
- MMC Support:
@@ -734,7 +734,7 @@ The following options need to be configured:
4th and following
BOOTP requests: delay 0 ... 8 sec
- CONFIG_BOOTP_ID_CACHE_SIZE
+ CFG_BOOTP_ID_CACHE_SIZE
BOOTP packets are uniquely identified using a 32-bit ID. The
server will copy the ID from client requests to responses and
@@ -747,7 +747,7 @@ The following options need to be configured:
time is too long, U-Boot will retransmit requests. In order
to allow earlier responses to still be accepted after these
retransmissions, U-Boot's BOOTP client keeps a small cache of
- IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
+ IDs. The CFG_BOOTP_ID_CACHE_SIZE controls the size of this
cache. The default is to keep IDs for up to four outstanding
requests. Increasing this will allow U-Boot to accept offers
from a BOOTP client in networks with unusually high latency.
@@ -832,11 +832,11 @@ The following options need to be configured:
status LED backend implementation. Define CONFIG_LED_STATUS_GPIO
to include the gpio_led driver in the U-Boot binary.
- CONFIG_GPIO_LED_INVERTED_TABLE
+ CFG_GPIO_LED_INVERTED_TABLE
Some GPIO connected LEDs may have inverted polarity in which
case the GPIO high value corresponds to LED off state and
GPIO low value corresponds to LED on state.
- In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+ In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined
with a list of GPIO LEDs that have inverted polarity.
- I2C Support:
@@ -993,7 +993,7 @@ The following options need to be configured:
SPI EEPROM, also an instance works with Crystal A/D and
D/As on the SACSng board)
- CONFIG_SYS_SPI_MXC_WAIT
+ CFG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
@@ -1023,7 +1023,7 @@ The following options need to be configured:
If defined, a function that provides delays in the FPGA
configuration driver.
- CONFIG_SYS_FPGA_CHECK_ERROR
+ CFG_SYS_FPGA_CHECK_ERROR
Check for configuration errors during FPGA bitfile
loading. For example, abort during Virtex II
@@ -1319,7 +1319,7 @@ Configuration Settings:
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
-- CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
+- CFG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default
width of the commands listed in the 'help' command output.
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5c45c2a5ed58..b0e867853375 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -91,8 +91,8 @@ static struct cpu_type cpu_type_list[] = {
#define EARLY_PGTABLE_SIZE 0x5000
static struct mm_region early_map[] = {
#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -101,26 +101,26 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
+ CFG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
/* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1_1,
+ { CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1,
+ CFG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ { CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
+ CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
+ CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
- { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1,
+ { CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1,
+ CFG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -131,31 +131,31 @@ static struct mm_region early_map[] = {
},
#ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -163,23 +163,23 @@ static struct mm_region early_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
+ CFG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
+ { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
+ CFG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -188,8 +188,8 @@ static struct mm_region early_map[] = {
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -199,8 +199,8 @@ static struct mm_region early_map[] = {
static struct mm_region final_map[] = {
#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -208,52 +208,52 @@ static struct mm_region final_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
+ CFG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2,
+ CFG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FSL_IFC_SIZE2,
+ { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FSL_IFC_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE,
+ { CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE,
+ CFG_SYS_FSL_MC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE,
+ { CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE,
+ CFG_SYS_FSL_NI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
/* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
+ CFG_SYS_FSL_QBMAN_SIZE_1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ { CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
+ CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
+ CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -295,29 +295,29 @@ static struct mm_region final_map[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE,
+ { CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE,
+ CFG_SYS_FSL_WRIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE,
+ { CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE,
+ CFG_SYS_FSL_AIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE,
+ { CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE,
+ CFG_SYS_FSL_PEBUF_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -328,8 +328,8 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -337,34 +337,34 @@ static struct mm_region final_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
+ CFG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
+ { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
+ CFG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE,
+ { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
+ CFG_SYS_FSL_QBMAN_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -385,8 +385,8 @@ static struct mm_region final_map[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -536,13 +536,13 @@ static inline void final_mmu_setup(void)
* table.
*/
switch (final_map[index].virt) {
- case CONFIG_SYS_FSL_DRAM_BASE1:
+ case CFG_SYS_FSL_DRAM_BASE1:
final_map[index].virt = gd->bd->bi_dram[0].start;
final_map[index].phys = gd->bd->bi_dram[0].start;
final_map[index].size = gd->bd->bi_dram[0].size;
break;
-#ifdef CONFIG_SYS_FSL_DRAM_BASE2
- case CONFIG_SYS_FSL_DRAM_BASE2:
+#ifdef CFG_SYS_FSL_DRAM_BASE2
+ case CFG_SYS_FSL_DRAM_BASE2:
#if (CONFIG_NR_DRAM_BANKS >= 2)
final_map[index].virt = gd->bd->bi_dram[1].start;
final_map[index].phys = gd->bd->bi_dram[1].start;
@@ -552,8 +552,8 @@ static inline void final_mmu_setup(void)
#endif
break;
#endif
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- case CONFIG_SYS_FSL_DRAM_BASE3:
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ case CFG_SYS_FSL_DRAM_BASE3:
#if (CONFIG_NR_DRAM_BANKS >= 3)
final_map[index].virt = gd->bd->bi_dram[2].start;
final_map[index].phys = gd->bd->bi_dram[2].start;
@@ -1566,7 +1566,7 @@ void update_early_mmu_table(void)
if (!gd->arch.tlb_addr)
return;
- if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
+ if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
CFG_SYS_SDRAM_BASE,
gd->ram_size,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 20f96713871a..444b56606a7d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,32 +8,32 @@
#define _FSL_LAYERSCAPE_CPU_H
#ifdef CONFIG_FSL_LSCH3
-#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CFG_SYS_FSL_CCSR_BASE 0x00000000
+#define CFG_SYS_FSL_CCSR_SIZE 0x10000000
#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CFG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CFG_SYS_FSL_IFC_BASE1 0x30000000
+#define CFG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CFG_SYS_FSL_IFC_SIZE1_1 0x400000
#endif
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CFG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CFG_SYS_FSL_IFC_BASE2 0x500000000
+#define CFG_SYS_FSL_IFC_SIZE2 0x100000000
#endif
-#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
-#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
-#define CONFIG_SYS_FSL_NI_BASE 0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CFG_SYS_FSL_DCSR_BASE 0x700000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CFG_SYS_FSL_MC_BASE 0x80c000000
+#define CFG_SYS_FSL_MC_SIZE 0x4000000
+#define CFG_SYS_FSL_NI_BASE 0x810000000
+#define CFG_SYS_FSL_NI_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_SIZE_1 0x4000000
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000
@@ -49,45 +49,45 @@
#define SYS_PCIE5_PHYS_SIZE 0x800000000
#define SYS_PCIE6_PHYS_SIZE 0x800000000
#endif
-#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CFG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CFG_SYS_FSL_AIOP1_SIZE 0x100000000
#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x4c00000000
#else
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x1c00000000
#endif
-#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CFG_SYS_FSL_PEBUF_SIZE 0x400000000
#ifdef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x2080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x1F80000000
+#define CFG_SYS_FSL_DRAM_BASE3 0x6000000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x2000000000
#else
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#endif
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
-#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
+#define CFG_SYS_FSL_CCSR_BASE 0x1000000
+#define CFG_SYS_FSL_CCSR_SIZE 0xf000000
+#define CFG_SYS_FSL_DCSR_BASE 0x20000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x4000000
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
-#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
-#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
-#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
+#define CFG_SYS_FSL_QSPI_SIZE 0x20000000
+#define CFG_SYS_FSL_IFC_BASE 0x60000000
+#define CFG_SYS_FSL_IFC_SIZE 0x20000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x500000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x10000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x880000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
+#define CFG_SYS_FSL_DRAM_BASE3 0x8800000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif
int fsl_qoriq_core_to_cluster(unsigned int core);
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index 979d5470e7a2..43ccae10bdf0 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -360,7 +360,7 @@ check_member(rk3288_msch, devtodev, 0x003c);
#define PCTL_STAT_MSK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
index 6f6c5c9954fb..0d29aefb646f 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -415,7 +415,7 @@ struct rk322x_base_params {
#define PCTL_STAT_MASK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index e3dcfdf37082..f0da46d863cf 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -14,7 +14,7 @@
#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
#ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
+#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c
index 5eb044731230..e90d5776703d 100644
--- a/arch/arm/mach-omap2/fdt-common.c
+++ b/arch/arm/mach-omap2/fdt-common.c
@@ -17,8 +17,8 @@
#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
#endif
int ft_hs_disable_rng(void *fdt, struct bd_info *bd)
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
index c4162420f3a7..a8c301c6c28f 100644
--- a/arch/arm/mach-omap2/omap5/fdt.c
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -19,8 +19,8 @@
#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
#endif
static u32 hs_irq_skip[] = {
@@ -92,7 +92,7 @@ static int ft_hs_fixup_crossbar(void *fdt, struct bd_info *bd)
}
#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
- (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+ (CFG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
{
const char *path;
@@ -116,7 +116,7 @@ static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
temp[0] = cpu_to_fdt32(0);
/* reservation size */
temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
- CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+ CFG_SECURE_RUNTIME_RESV_SRAM_SZ));
fdt_delprop(fdt, offs, "reg");
ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
if (ret < 0) {
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
index f2f8ce95992c..d241652641fb 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
@@ -22,78 +22,78 @@
#define mstp_setclrbits_le32(addr, set, clear) \
mstp_setclrbits(le32, addr, set, clear)
-#ifndef CONFIG_SMSTP0_ENA
-#define CONFIG_SMSTP0_ENA 0x00
+#ifndef CFG_SMSTP0_ENA
+#define CFG_SMSTP0_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP1_ENA
-#define CONFIG_SMSTP1_ENA 0x00
+#ifndef CFG_SMSTP1_ENA
+#define CFG_SMSTP1_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP2_ENA
-#define CONFIG_SMSTP2_ENA 0x00
+#ifndef CFG_SMSTP2_ENA
+#define CFG_SMSTP2_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP3_ENA
-#define CONFIG_SMSTP3_ENA 0x00
+#ifndef CFG_SMSTP3_ENA
+#define CFG_SMSTP3_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP4_ENA
-#define CONFIG_SMSTP4_ENA 0x00
+#ifndef CFG_SMSTP4_ENA
+#define CFG_SMSTP4_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP5_ENA
-#define CONFIG_SMSTP5_ENA 0x00
+#ifndef CFG_SMSTP5_ENA
+#define CFG_SMSTP5_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP6_ENA
-#define CONFIG_SMSTP6_ENA 0x00
+#ifndef CFG_SMSTP6_ENA
+#define CFG_SMSTP6_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP7_ENA
-#define CONFIG_SMSTP7_ENA 0x00
+#ifndef CFG_SMSTP7_ENA
+#define CFG_SMSTP7_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP8_ENA
-#define CONFIG_SMSTP8_ENA 0x00
+#ifndef CFG_SMSTP8_ENA
+#define CFG_SMSTP8_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP9_ENA
-#define CONFIG_SMSTP9_ENA 0x00
+#ifndef CFG_SMSTP9_ENA
+#define CFG_SMSTP9_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP10_ENA
-#define CONFIG_SMSTP10_ENA 0x00
+#ifndef CFG_SMSTP10_ENA
+#define CFG_SMSTP10_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP11_ENA
-#define CONFIG_SMSTP11_ENA 0x00
+#ifndef CFG_SMSTP11_ENA
+#define CFG_SMSTP11_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP0_ENA
-#define CONFIG_RMSTP0_ENA 0x00
+#ifndef CFG_RMSTP0_ENA
+#define CFG_RMSTP0_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP1_ENA
-#define CONFIG_RMSTP1_ENA 0x00
+#ifndef CFG_RMSTP1_ENA
+#define CFG_RMSTP1_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP2_ENA
-#define CONFIG_RMSTP2_ENA 0x00
+#ifndef CFG_RMSTP2_ENA
+#define CFG_RMSTP2_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP3_ENA
-#define CONFIG_RMSTP3_ENA 0x00
+#ifndef CFG_RMSTP3_ENA
+#define CFG_RMSTP3_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP4_ENA
-#define CONFIG_RMSTP4_ENA 0x00
+#ifndef CFG_RMSTP4_ENA
+#define CFG_RMSTP4_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP5_ENA
-#define CONFIG_RMSTP5_ENA 0x00
+#ifndef CFG_RMSTP5_ENA
+#define CFG_RMSTP5_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP6_ENA
-#define CONFIG_RMSTP6_ENA 0x00
+#ifndef CFG_RMSTP6_ENA
+#define CFG_RMSTP6_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP7_ENA
-#define CONFIG_RMSTP7_ENA 0x00
+#ifndef CFG_RMSTP7_ENA
+#define CFG_RMSTP7_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP8_ENA
-#define CONFIG_RMSTP8_ENA 0x00
+#ifndef CFG_RMSTP8_ENA
+#define CFG_RMSTP8_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP9_ENA
-#define CONFIG_RMSTP9_ENA 0x00
+#ifndef CFG_RMSTP9_ENA
+#define CFG_RMSTP9_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP10_ENA
-#define CONFIG_RMSTP10_ENA 0x00
+#ifndef CFG_RMSTP10_ENA
+#define CFG_RMSTP10_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP11_ENA
-#define CONFIG_RMSTP11_ENA 0x00
+#ifndef CFG_RMSTP11_ENA
+#define CFG_RMSTP11_ENA 0x00
#endif
struct mstp_ctl {
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 6ae254e99af5..fcae65b2e5a1 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -198,7 +198,7 @@ enum {
/* PCTL_STAT */
INIT_MEM = 0,
CONFIG,
- CONFIG_REQ,
+ CFG_REQ,
ACCESS,
ACCESS_REQ,
LOW_POWER,
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
index be801d108e37..94ce762e01f5 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
@@ -34,7 +34,7 @@ void wb_start(void)
u32 reg;
/* enable JTAG & TBE */
- writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
+ writel(CFG_CTL_TBE | CFG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */
asm volatile (
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
index 19a476b89571..f300fe66254b 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
@@ -19,8 +19,8 @@
#define USEC_CFG_DIVISOR_MASK 0xffff
-#define CONFIG_CTL_TBE (1 << 7)
-#define CONFIG_CTL_JTAG (1 << 6)
+#define CFG_CTL_TBE (1 << 7)
+#define CFG_CTL_JTAG (1 << 6)
#define CPU_RST (1 << 0)
#define CLK_ENB_CPU (1 << 0)
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index b554c51fcbe3..331288e00602 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -13,7 +13,7 @@
int interrupt_init(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrl0, 0x1);
@@ -25,10 +25,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
- clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+ clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
#endif
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index 35ed1e7901ba..e8a1e132d278 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -37,10 +37,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+ intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
- setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
+ setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
@@ -49,7 +49,7 @@ void dtimer_intr_setup(void)
defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
#if defined(CONFIG_M5208)
@@ -66,11 +66,11 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
clrbits_be32(&intp->imrl0, 0x00000001);
- clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+ clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -87,7 +87,7 @@ int interrupt_init(void)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
- mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
+ mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c
index 2659e3478f04..11686202dc73 100644
--- a/arch/m68k/cpu/mcf530x/interrupts.c
+++ b/arch/m68k/cpu/mcf530x/interrupts.c
@@ -24,6 +24,6 @@ void dtimer_intr_setup(void)
/* clearing TIMER2 mask, so enabling the related interrupt */
out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
/* set TIMER2 interrupt priority */
- out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+ out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI);
}
#endif
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index 8f2df452baee..64e04664a52b 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -13,7 +13,7 @@
int interrupt_init(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrh0, 0xffffffff);
@@ -26,9 +26,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
- clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+ out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
}
#endif
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index 5a6a88cd5713..ea0cf87990c9 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -16,7 +16,7 @@
int interrupt_init(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
setbits_be32(&intp->imrh0, 0xffffffff);
@@ -29,9 +29,9 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
- clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+ out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
}
#endif
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index c05356fc930c..8ed2b4dbab47 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -11,21 +11,21 @@
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
defined(CONFIG_MCF52x2)
-#define CONFIG_CF_V2
+#define CFG_CF_V2
#endif
#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
defined(CONFIG_MCF5301x)
-#define CONFIG_CF_V3
+#define CFG_CF_V3
#endif
#if defined(CONFIG_MCF5441x)
-#define CONFIG_CF_V4E /* Four Extra ACRn */
+#define CFG_CF_V4E /* Four Extra ACRn */
#endif
/* ***** CACR ***** */
/* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
#define CF_CACR_CENB (1 << 31)
#define CF_CACR_CPD (1 << 28)
@@ -46,10 +46,10 @@
#define CF_CACR_EUSP (1 << 4)
#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
-#endif /* CONFIG_CF_V2 */
+#endif /* CFG_CF_V2 */
/* V3 Core */
-#ifdef CONFIG_CF_V3
+#ifdef CFG_CF_V3
#define CF_CACR_EC (1 << 31)
#define CF_CACR_ESB (1 << 29)
@@ -65,10 +65,10 @@
#define CF_CACR_DW (1 << 5)
#define CF_CACR_EUSP (1 << 4)
-#endif /* CONFIG_CF_V3 */
+#endif /* CFG_CF_V3 */
/* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
#define CF_CACR_DEC (1 << 31)
#define CF_CACR_DW (1 << 30)
@@ -116,7 +116,7 @@
#define CF_ACR_WP (1 << 2)
/* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
#define CF_ACR_CM (1 << 6)
#define CF_ACR_BWE (1 << 5)
#else
@@ -126,10 +126,10 @@
#define CF_ACR_CM_CB (1 << 5)
#define CF_ACR_CM_P (2 << 5)
#define CF_ACR_CM_IP (3 << 5)
-#endif /* CONFIG_CF_V2 */
+#endif /* CFG_CF_V2 */
/* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
#define CF_ACR_AMM (1 << 10)
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */
@@ -159,24 +159,24 @@
#define CFG_SYS_CACHE_ACR2 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR3
-#define CONFIG_SYS_CACHE_ACR3 0
+#ifndef CFG_SYS_CACHE_ACR3
+#define CFG_SYS_CACHE_ACR3 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR4
-#define CONFIG_SYS_CACHE_ACR4 0
+#ifndef CFG_SYS_CACHE_ACR4
+#define CFG_SYS_CACHE_ACR4 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR5
-#define CONFIG_SYS_CACHE_ACR5 0
+#ifndef CFG_SYS_CACHE_ACR5
+#define CFG_SYS_CACHE_ACR5 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR6
-#define CONFIG_SYS_CACHE_ACR6 0
+#ifndef CFG_SYS_CACHE_ACR6
+#define CFG_SYS_CACHE_ACR6 0
#endif
-#ifndef CONFIG_SYS_CACHE_ACR7
-#define CONFIG_SYS_CACHE_ACR7 0
+#ifndef CFG_SYS_CACHE_ACR7
+#define CFG_SYS_CACHE_ACR7 0
#endif
#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h
index f7f0f07d30f0..3f7c458ef083 100644
--- a/arch/m68k/include/asm/coldfire/intctrl.h
+++ b/arch/m68k/include/asm/coldfire/intctrl.h
@@ -12,7 +12,7 @@
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
defined(CONFIG_M547x)
-# define CONFIG_SYS_CF_INTC_REG1
+# define CFG_SYS_CF_INTC_REG1
#endif
typedef struct int0_ctrl {
@@ -23,7 +23,7 @@ typedef struct int0_ctrl {
u32 imrl0; /* 0x0C Mask Low */
u32 frch0; /* 0x10 Force High */
u32 frcl0; /* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
@@ -64,7 +64,7 @@ typedef struct int1_ctrl {
u32 imrl1; /* 0x0C Mask Low */
u32 frch1; /* 0x10 Force High */
u32 frcl1; /* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1[19]; /* 0x1a - 0x3c */
@@ -192,7 +192,7 @@ typedef struct intgack_ctrl1 {
#define INTC_IACKLPR_PRI(x) ((x) & 0x0F)
#define INTC_IACKLPR_PRI_MASK (0xF0)
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
#define INTC_ICR_IL(x) (((x) & 0x07) << 3)
#define INTC_ICR_IL_MASK (0xC7)
#define INTC_ICR_IP(x) ((x) & 0x07)
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 0c23744a867e..8207c8d5b734 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -13,65 +13,65 @@
#include <asm/immap_520x.h>
#include <asm/m520x.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (6)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M520x */
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5235 */
#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS (64)
+#define CFG_SYS_INTR_BASE (MMAP_INTC)
+#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO (31)
-#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRINTR_NO (31)
+#define CFG_SYS_TMRINTR_MASK (0x00000400)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5249 */
@@ -80,21 +80,21 @@
#include <asm/m5249.h>
#include <asm/m5253.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS (64)
+#define CFG_SYS_INTR_BASE (MMAP_INTC)
+#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO (27)
-#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRINTR_NO (27)
+#define CFG_SYS_TMRINTR_MASK (0x00000400)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif /* CONFIG_M5253 */
@@ -102,43 +102,43 @@
#include <asm/immap_5271.h>
#include <asm/m5271.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS (64)
+#define CFG_SYS_INTR_BASE (MMAP_INTC)
+#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
-#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
-#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
-#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
-#define CONFIG_SYS_TMRINTR_PEND (0)
-#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
+#define CFG_SYS_TMR_BASE (MMAP_TMR3)
+#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
+#define CFG_SYS_TMRINTR_NO (INT_TMR3)
+#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
+#define CFG_SYS_TMRINTR_PEND (0)
+#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5272 */
@@ -146,21 +146,21 @@
#include <asm/immap_5275.h>
#include <asm/m5275.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (192)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (192)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (0x1E)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5275 */
@@ -168,21 +168,21 @@
#include <asm/immap_5282.h>
#include <asm/m5282.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5282 */
@@ -190,23 +190,23 @@
#include <asm/immap_5307.h>
#include <asm/m5307.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+#define CFG_SYS_UART_BASE (MMAP_UART0 + \
(CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS (64)
+#define CFG_SYS_INTR_BASE (MMAP_INTC)
+#define CFG_SYS_NUM_IRQS (64)
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
- (CONFIG_SYS_INTR_BASE))->ipr)
-#define CONFIG_SYS_TMRINTR_NO (31)
-#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
+ (CFG_SYS_INTR_BASE))->ipr)
+#define CFG_SYS_TMRINTR_NO (31)
+#define CFG_SYS_TMRINTR_MASK (0x00000400)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif /* CONFIG_M5307 */
@@ -214,44 +214,44 @@
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (6)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5301x */
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (6)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
#if defined(CONFIG_M54418)
@@ -259,10 +259,10 @@
#include <asm/m5441x.h>
#if (CFG_SYS_UART_PORT < 4)
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+#define CFG_SYS_UART_BASE (MMAP_UART0 + \
(CFG_SYS_UART_PORT * 0x4000))
#else
-#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
+#define CFG_SYS_UART_BASE (MMAP_UART4 + \
((CFG_SYS_UART_PORT - 4) * 0x4000))
#endif
@@ -270,18 +270,18 @@
/* Timer */
#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (6)
+#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (192)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (192)
#endif /* CONFIG_M54418 */
@@ -304,21 +304,21 @@
#define FEC1_TX_INIT 31
#endif
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
+#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
-#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
+#define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
+#define CFG_SYS_TMR_BASE (MMAP_SLT0)
+#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
+#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
+#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI (0x1E)
+#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
+#define CFG_SYS_INTR_BASE (MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_SYS_PCI_BAR0 (0x40000000)
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 4ddda69f5a38..57e5632fdb5b 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -33,12 +33,12 @@ void icache_enable(void)
*cf_icache_status = 1;
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
- __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
-#if defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
- __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+ __asm__ __volatile__("movec %0, %%acr3"::"r"(CFG_SYS_CACHE_ACR3));
+#if defined(CFG_CF_V4E)
+ __asm__ __volatile__("movec %0, %%acr6"::"r"(CFG_SYS_CACHE_ACR6));
+ __asm__ __volatile__("movec %0, %%acr7"::"r"(CFG_SYS_CACHE_ACR7));
#endif
#else
__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
@@ -55,10 +55,10 @@ void icache_disable(void)
*cf_icache_status = 0;
icache_invalid();
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
#endif
@@ -88,12 +88,12 @@ void dcache_enable(void)
dcache_invalid();
*cf_dcache_status = 1;
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
-#if defined(CONFIG_CF_V4E)
- __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
- __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+#if defined(CFG_CF_V4E)
+ __asm__ __volatile__("movec %0, %%acr4"::"r"(CFG_SYS_CACHE_ACR4));
+ __asm__ __volatile__("movec %0, %%acr5"::"r"(CFG_SYS_CACHE_ACR5));
#endif
#endif
@@ -109,10 +109,10 @@ void dcache_disable(void)
__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
#endif
@@ -121,7 +121,7 @@ void dcache_disable(void)
void dcache_invalid(void)
{
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
u32 temp;
temp = CFG_SYS_DCACHE_INV;
diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c
index 1caef61d20e9..799daab5612d 100644
--- a/arch/m68k/lib/interrupts.c
+++ b/arch/m68k/lib/interrupts.c
@@ -14,7 +14,7 @@
#include <asm/immap.h>
#include <asm/ptrace.h>
-#define NR_IRQS (CONFIG_SYS_NUM_IRQS)
+#define NR_IRQS (CFG_SYS_NUM_IRQS)
/*
* Interrupt vector functions.
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index cd7437b3e22e..2ce69088d94c 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -21,23 +21,23 @@ DECLARE_GLOBAL_DATA_PTR;
static volatile ulong timestamp = 0;
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#ifndef CFG_SYS_WATCHDOG_FREQ
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
#if defined(CONFIG_MCFTMR)
-#ifndef CONFIG_SYS_UDELAY_BASE
+#ifndef CFG_SYS_UDELAY_BASE
# error "uDelay base not defined!"
#endif
-#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
+#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
#endif
extern void dtimer_intr_setup(void);
void __udelay(unsigned long usec)
{
- volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
uint start, now, tmp;
while (usec > 0) {
@@ -52,7 +52,7 @@ void __udelay(unsigned long usec)
timerp->tcn = 0;
/* set period to 1 us */
timerp->tmr =
- CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
+ CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
DTIM_DTMR_RST_EN;
start = now = timerp->tcn;
@@ -63,15 +63,15 @@ void __udelay(unsigned long usec)
void dtimer_interrupt(void *not_used)
{
- volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
/* check for timer interrupt asserted */
- if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
+ if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
timestamp++;
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
- if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
+ if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
schedule();
}
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
@@ -81,7 +81,7 @@ void dtimer_interrupt(void *not_used)
int timer_init(void)
{
- volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+ volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
timestamp = 0;
@@ -92,7 +92,7 @@ int timer_init(void)
timerp->tmr = DTIM_DTMR_RST_RST;
/* initialize and enable timer interrupt */
- irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
+ irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
timerp->tcn = 0;
timerp->trr = 1000; /* Interrupt every ms */
@@ -100,7 +100,7 @@ int timer_init(void)
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
- timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
+ timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
return 0;
diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S
index 7063f32610b7..d2f9c031cbae 100644
--- a/arch/mips/mach-mtmips/mt7621/spl/start.S
+++ b/arch/mips/mach-mtmips/mt7621/spl/start.S
@@ -17,8 +17,8 @@
#include "../mt7621.h"
#include "dram.h"
-#ifndef CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
+#ifndef CFG_SYS_INIT_SP_ADDR
+#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \
CFG_SYS_INIT_SP_OFFSET)
#endif
@@ -31,7 +31,7 @@
.macro setup_stack_gd
li t0, -16
- PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
+ PTR_LI t1, CFG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd
@@ -201,7 +201,7 @@ ENTRY(_start)
#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
/* Set malloc base */
- li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
+ li t0, (CFG_SYS_INIT_SP_ADDR + 15) & (~15)
PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/bats/bats.h b/arch/powerpc/cpu/mpc83xx/bats/bats.h
index f0754c2351ef..2629cd5eab80 100644
--- a/arch/powerpc/cpu/mpc83xx/bats/bats.h
+++ b/arch/powerpc/cpu/mpc83xx/bats/bats.h
@@ -1,223 +1,223 @@
#ifdef CONFIG_BAT0
-#define CONFIG_SYS_IBAT0L (\
+#define CFG_SYS_IBAT0L (\
(CONFIG_BAT0_BASE) |\
(CONFIG_BAT0_PAGE_PROTECTION) |\
(CONFIG_BAT0_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT0U (\
+#define CFG_SYS_IBAT0U (\
(CONFIG_BAT0_BASE) |\
(CONFIG_BAT0_LENGTH) |\
(CONFIG_BAT0_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT0L (\
+#define CFG_SYS_DBAT0L (\
(CONFIG_BAT0_BASE) |\
(CONFIG_BAT0_PAGE_PROTECTION) |\
(CONFIG_BAT0_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT0U (\
+#define CFG_SYS_DBAT0U (\
(CONFIG_BAT0_BASE) |\
(CONFIG_BAT0_LENGTH) |\
(CONFIG_BAT0_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT0L (0)
-#define CONFIG_SYS_IBAT0U (0)
-#define CONFIG_SYS_DBAT0L (0)
-#define CONFIG_SYS_DBAT0U (0)
+#define CFG_SYS_IBAT0L (0)
+#define CFG_SYS_IBAT0U (0)
+#define CFG_SYS_DBAT0L (0)
+#define CFG_SYS_DBAT0U (0)
#endif /* CONFIG_BAT0 */
#ifdef CONFIG_BAT1
-#define CONFIG_SYS_IBAT1L (\
+#define CFG_SYS_IBAT1L (\
(CONFIG_BAT1_BASE) |\
(CONFIG_BAT1_PAGE_PROTECTION) |\
(CONFIG_BAT1_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT1U (\
+#define CFG_SYS_IBAT1U (\
(CONFIG_BAT1_BASE) |\
(CONFIG_BAT1_LENGTH) |\
(CONFIG_BAT1_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT1L (\
+#define CFG_SYS_DBAT1L (\
(CONFIG_BAT1_BASE) |\
(CONFIG_BAT1_PAGE_PROTECTION) |\
(CONFIG_BAT1_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT1U (\
+#define CFG_SYS_DBAT1U (\
(CONFIG_BAT1_BASE) |\
(CONFIG_BAT1_LENGTH) |\
(CONFIG_BAT1_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT1L (0)
-#define CONFIG_SYS_IBAT1U (0)
-#define CONFIG_SYS_DBAT1L (0)
-#define CONFIG_SYS_DBAT1U (0)
+#define CFG_SYS_IBAT1L (0)
+#define CFG_SYS_IBAT1U (0)
+#define CFG_SYS_DBAT1L (0)
+#define CFG_SYS_DBAT1U (0)
#endif /* CONFIG_BAT1 */
#ifdef CONFIG_BAT2
-#define CONFIG_SYS_IBAT2L (\
+#define CFG_SYS_IBAT2L (\
(CONFIG_BAT2_BASE) |\
(CONFIG_BAT2_PAGE_PROTECTION) |\
(CONFIG_BAT2_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT2U (\
+#define CFG_SYS_IBAT2U (\
(CONFIG_BAT2_BASE) |\
(CONFIG_BAT2_LENGTH) |\
(CONFIG_BAT2_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT2L (\
+#define CFG_SYS_DBAT2L (\
(CONFIG_BAT2_BASE) |\
(CONFIG_BAT2_PAGE_PROTECTION) |\
(CONFIG_BAT2_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT2U (\
+#define CFG_SYS_DBAT2U (\
(CONFIG_BAT2_BASE) |\
(CONFIG_BAT2_LENGTH) |\
(CONFIG_BAT2_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT2L (0)
-#define CONFIG_SYS_IBAT2U (0)
-#define CONFIG_SYS_DBAT2L (0)
-#define CONFIG_SYS_DBAT2U (0)
+#define CFG_SYS_IBAT2L (0)
+#define CFG_SYS_IBAT2U (0)
+#define CFG_SYS_DBAT2L (0)
+#define CFG_SYS_DBAT2U (0)
#endif /* CONFIG_BAT2 */
#ifdef CONFIG_BAT3
-#define CONFIG_SYS_IBAT3L (\
+#define CFG_SYS_IBAT3L (\
(CONFIG_BAT3_BASE) |\
(CONFIG_BAT3_PAGE_PROTECTION) |\
(CONFIG_BAT3_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT3U (\
+#define CFG_SYS_IBAT3U (\
(CONFIG_BAT3_BASE) |\
(CONFIG_BAT3_LENGTH) |\
(CONFIG_BAT3_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT3L (\
+#define CFG_SYS_DBAT3L (\
(CONFIG_BAT3_BASE) |\
(CONFIG_BAT3_PAGE_PROTECTION) |\
(CONFIG_BAT3_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT3U (\
+#define CFG_SYS_DBAT3U (\
(CONFIG_BAT3_BASE) |\
(CONFIG_BAT3_LENGTH) |\
(CONFIG_BAT3_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT3L (0)
-#define CONFIG_SYS_IBAT3U (0)
-#define CONFIG_SYS_DBAT3L (0)
-#define CONFIG_SYS_DBAT3U (0)
+#define CFG_SYS_IBAT3L (0)
+#define CFG_SYS_IBAT3U (0)
+#define CFG_SYS_DBAT3L (0)
+#define CFG_SYS_DBAT3U (0)
#endif /* CONFIG_BAT3 */
#ifdef CONFIG_BAT4
-#define CONFIG_SYS_IBAT4L (\
+#define CFG_SYS_IBAT4L (\
(CONFIG_BAT4_BASE) |\
(CONFIG_BAT4_PAGE_PROTECTION) |\
(CONFIG_BAT4_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT4U (\
+#define CFG_SYS_IBAT4U (\
(CONFIG_BAT4_BASE) |\
(CONFIG_BAT4_LENGTH) |\
(CONFIG_BAT4_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT4L (\
+#define CFG_SYS_DBAT4L (\
(CONFIG_BAT4_BASE) |\
(CONFIG_BAT4_PAGE_PROTECTION) |\
(CONFIG_BAT4_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT4U (\
+#define CFG_SYS_DBAT4U (\
(CONFIG_BAT4_BASE) |\
(CONFIG_BAT4_LENGTH) |\
(CONFIG_BAT4_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-#define CONFIG_SYS_DBAT4L (0)
-#define CONFIG_SYS_DBAT4U (0)
+#define CFG_SYS_IBAT4L (0)
+#define CFG_SYS_IBAT4U (0)
+#define CFG_SYS_DBAT4L (0)
+#define CFG_SYS_DBAT4U (0)
#endif /* CONFIG_BAT4 */
#ifdef CONFIG_BAT5
-#define CONFIG_SYS_IBAT5L (\
+#define CFG_SYS_IBAT5L (\
(CONFIG_BAT5_BASE) |\
(CONFIG_BAT5_PAGE_PROTECTION) |\
(CONFIG_BAT5_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT5U (\
+#define CFG_SYS_IBAT5U (\
(CONFIG_BAT5_BASE) |\
(CONFIG_BAT5_LENGTH) |\
(CONFIG_BAT5_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT5L (\
+#define CFG_SYS_DBAT5L (\
(CONFIG_BAT5_BASE) |\
(CONFIG_BAT5_PAGE_PROTECTION) |\
(CONFIG_BAT5_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT5U (\
+#define CFG_SYS_DBAT5U (\
(CONFIG_BAT5_BASE) |\
(CONFIG_BAT5_LENGTH) |\
(CONFIG_BAT5_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_DBAT5L (0)
-#define CONFIG_SYS_DBAT5U (0)
+#define CFG_SYS_IBAT5L (0)
+#define CFG_SYS_IBAT5U (0)
+#define CFG_SYS_DBAT5L (0)
+#define CFG_SYS_DBAT5U (0)
#endif /* CONFIG_BAT5 */
#ifdef CONFIG_BAT6
-#define CONFIG_SYS_IBAT6L (\
+#define CFG_SYS_IBAT6L (\
(CONFIG_BAT6_BASE) |\
(CONFIG_BAT6_PAGE_PROTECTION) |\
(CONFIG_BAT6_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT6U (\
+#define CFG_SYS_IBAT6U (\
(CONFIG_BAT6_BASE) |\
(CONFIG_BAT6_LENGTH) |\
(CONFIG_BAT6_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT6L (\
+#define CFG_SYS_DBAT6L (\
(CONFIG_BAT6_BASE) |\
(CONFIG_BAT6_PAGE_PROTECTION) |\
(CONFIG_BAT6_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT6U (\
+#define CFG_SYS_DBAT6U (\
(CONFIG_BAT6_BASE) |\
(CONFIG_BAT6_LENGTH) |\
(CONFIG_BAT6_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT6L (0)
-#define CONFIG_SYS_IBAT6U (0)
-#define CONFIG_SYS_DBAT6L (0)
-#define CONFIG_SYS_DBAT6U (0)
+#define CFG_SYS_IBAT6L (0)
+#define CFG_SYS_IBAT6U (0)
+#define CFG_SYS_DBAT6L (0)
+#define CFG_SYS_DBAT6U (0)
#endif /* CONFIG_BAT6 */
#ifdef CONFIG_BAT7
-#define CONFIG_SYS_IBAT7L (\
+#define CFG_SYS_IBAT7L (\
(CONFIG_BAT7_BASE) |\
(CONFIG_BAT7_PAGE_PROTECTION) |\
(CONFIG_BAT7_WIMG_ICACHE) \
)
-#define CONFIG_SYS_IBAT7U (\
+#define CFG_SYS_IBAT7U (\
(CONFIG_BAT7_BASE) |\
(CONFIG_BAT7_LENGTH) |\
(CONFIG_BAT7_VALID_BITS) \
)
-#define CONFIG_SYS_DBAT7L (\
+#define CFG_SYS_DBAT7L (\
(CONFIG_BAT7_BASE) |\
(CONFIG_BAT7_PAGE_PROTECTION) |\
(CONFIG_BAT7_WIMG_DCACHE) \
)
-#define CONFIG_SYS_DBAT7U (\
+#define CFG_SYS_DBAT7U (\
(CONFIG_BAT7_BASE) |\
(CONFIG_BAT7_LENGTH) |\
(CONFIG_BAT7_VALID_BITS) \
)
#else
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-#define CONFIG_SYS_DBAT7L (0)
-#define CONFIG_SYS_DBAT7U (0)
+#define CFG_SYS_IBAT7L (0)
+#define CFG_SYS_IBAT7U (0)
+#define CFG_SYS_DBAT7L (0)
+#define CFG_SYS_DBAT7U (0)
#endif /* CONFIG_BAT7 */
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 63c2729411c7..2af5c89ae522 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -208,24 +208,24 @@ void cpu_init_f (volatile immap_t * im)
init_early_memctl_regs();
/* Local Access window setup */
-#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
- im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
- im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
+#if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM)
+ im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM;
+ im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM;
#else
-#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#error CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
- im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
- im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
+#if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM)
+ im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM;
+ im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
- im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
- im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
+#if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM)
+ im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM;
+ im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
- im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
- im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
+#if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM)
+ im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM;
+ im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
diff --git a/arch/powerpc/cpu/mpc83xx/hid/hid.h b/arch/powerpc/cpu/mpc83xx/hid/hid.h
index 9f5260c012c7..089d1d77f0b9 100644
--- a/arch/powerpc/cpu/mpc83xx/hid/hid.h
+++ b/arch/powerpc/cpu/mpc83xx/hid/hid.h
@@ -1,4 +1,4 @@
-#define CONFIG_SYS_HID0_FINAL ( \
+#define CFG_SYS_HID0_FINAL ( \
CONFIG_HID0_FINAL_ABE_BIT |\
CONFIG_HID0_FINAL_CLKOUT |\
CONFIG_HID0_FINAL_DCE_BIT |\
@@ -24,7 +24,7 @@
CONFIG_HID0_FINAL_SLEEP_BIT \
)
-#define CONFIG_SYS_HID0_INIT ( \
+#define CFG_SYS_HID0_INIT ( \
CONFIG_HID0_INIT_ABE_BIT |\
CONFIG_HID0_INIT_CLKOUT |\
CONFIG_HID0_INIT_DCE_BIT |\
@@ -50,12 +50,12 @@
#ifdef CONFIG_TARGET_IDS8313
/* IDS8313 defines a reserved bit; keep to not break compatibility */
-#define CONFIG_HID2_SPECIAL 0x00020000
+#define CFG_HID2_SPECIAL 0x00020000
#else
-#define CONFIG_HID2_SPECIAL 0x0
+#define CFG_HID2_SPECIAL 0x0
#endif
-#define CONFIG_SYS_HID2 ( \
+#define CFG_SYS_HID2 ( \
CONFIG_HID2_LET_BIT |\
CONFIG_HID2_IFEB_BIT |\
CONFIG_HID2_MESISTATE_BIT |\
@@ -68,5 +68,5 @@
CONFIG_HID2_IWLCK |\
CONFIG_HID2_ICWP_BIT |\
CONFIG_HID2_DWLCK |\
- CONFIG_HID2_SPECIAL \
+ CFG_HID2_SPECIAL \
)
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
index 0f3426789181..7f8787ffb0de 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
@@ -1,4 +1,4 @@
-#define CONFIG_SYS_HRCW_LOW (\
+#define CFG_SYS_HRCW_LOW (\
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
@@ -9,7 +9,7 @@
(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
)
-#define CONFIG_SYS_HRCW_HIGH (\
+#define CFG_SYS_HRCW_HIGH (\
(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
diff --git a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
index 6972afcc2c70..082b2b9c9a56 100644
--- a/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
+++ b/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
@@ -1,55 +1,55 @@
#if defined(CONFIG_LBLAW0)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+#define CFG_SYS_LBLAWBAR0_PRELIM \
CONFIG_LBLAW0_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+#define CFG_SYS_LBLAWAR0_PRELIM (\
CONFIG_LBLAW0_ENABLE_BIT |\
CONFIG_LBLAW0_LENGTH \
)
#endif
#if defined(CONFIG_LBLAW1)
-#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+#define CFG_SYS_LBLAWBAR1_PRELIM \
CONFIG_LBLAW1_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+#define CFG_SYS_LBLAWAR1_PRELIM (\
CONFIG_LBLAW1_ENABLE_BIT |\
CONFIG_LBLAW1_LENGTH \
)
#endif
#if defined(CONFIG_LBLAW2)
-#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+#define CFG_SYS_LBLAWBAR2_PRELIM \
CONFIG_LBLAW2_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+#define CFG_SYS_LBLAWAR2_PRELIM (\
CONFIG_LBLAW2_ENABLE_BIT |\
CONFIG_LBLAW2_LENGTH \
)
#endif
#if defined(CONFIG_LBLAW3)
-#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+#define CFG_SYS_LBLAWBAR3_PRELIM \
CONFIG_LBLAW3_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+#define CFG_SYS_LBLAWAR3_PRELIM (\
CONFIG_LBLAW3_ENABLE_BIT |\
CONFIG_LBLAW3_LENGTH \
)
#endif
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR0_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR0_PRELIM
#endif
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR1_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR1_PRELIM
#endif
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR2_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR2_PRELIM
#endif
#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#define CFG_SYS_NAND_LBLAWBAR_PRELIM CFG_SYS_LBLAWBAR3_PRELIM
+#define CFG_SYS_NAND_LBLAWAR_PRELIM CFG_SYS_LBLAWAR3_PRELIM
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 4f982b8303ae..6da8fc4381d1 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -66,8 +66,8 @@ void board_add_ram_info(int use_default)
}
#ifdef CONFIG_SPD_EEPROM
-#ifndef CONFIG_SYS_READ_SPD
-#define CONFIG_SYS_READ_SPD i2c_read
+#ifndef CFG_SYS_READ_SPD
+#define CFG_SYS_READ_SPD i2c_read
#endif
#ifndef SPD_EEPROM_OFFSET
#define SPD_EEPROM_OFFSET 0
@@ -167,7 +167,7 @@ long int spd_sdram()
isync();
/* Read SPD parameters with I2C */
- CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
+ CFG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 7cc0383afbfc..b55bfaffcaed 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -73,14 +73,14 @@ void cpu_init_f (volatile immap_t * im)
#if defined(CFG_SYS_NAND_BR_PRELIM) \
&& defined(CFG_SYS_NAND_OR_PRELIM) \
- && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
- && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+ && defined(CFG_SYS_NAND_LBLAWBAR_PRELIM) \
+ && defined(CFG_SYS_NAND_LBLAWAR_PRELIM)
set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM);
- im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
- im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
+ im->sysconf.lblaw[0].bar = CFG_SYS_NAND_LBLAWBAR_PRELIM;
+ im->sysconf.lblaw[0].ar = CFG_SYS_NAND_LBLAWAR_PRELIM;
#else
-#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CFG_SYS_NAND_LBLAWBAR_PRELIM & CFG_SYS_NAND_LBLAWAR_PRELIM must be defined
#endif
}
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 52326f0ec155..e3878e431fbe 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -46,7 +46,7 @@
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_SYS_FLASHBOOT
+#define CFG_SYS_FLASHBOOT
#endif
/*
@@ -81,8 +81,8 @@
.fill 8,1,(((w)>> 8)&0xff); \
.fill 8,1,(((w) )&0xff)
- _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
- _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
+ _HRCW_TABLE_ENTRY(CFG_SYS_HRCW_LOW)
+ _HRCW_TABLE_ENTRY(CFG_SYS_HRCW_HIGH)
/*
* Magic number and version string - put it after the HRCW since it
@@ -180,7 +180,7 @@ _start: /* time t 0 */
bl init_e300_core
-#ifdef CONFIG_SYS_FLASHBOOT
+#ifdef CFG_SYS_FLASHBOOT
/* Inflate flash location so it appears everywhere, calculate */
/* the absolute address in final location of the FLASH, jump */
@@ -196,7 +196,7 @@ in_flash:
#if 1 /* Remapping flash with LAW0. */
bl remap_flash_by_law0
#endif
-#endif /* CONFIG_SYS_FLASHBOOT */
+#endif /* CFG_SYS_FLASHBOOT */
/* setup the bats */
bl setup_bats
@@ -525,18 +525,18 @@ init_e300_core: /* time t 10 */
/* - force invalidation of data and instruction caches */
/*------------------------------------------------------*/
- lis r3, CONFIG_SYS_HID0_INIT at h
- ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
+ lis r3, CFG_SYS_HID0_INIT at h
+ ori r3, r3, (CFG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
SYNC
mtspr HID0, r3
- lis r3, CONFIG_SYS_HID0_FINAL at h
- ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
+ lis r3, CFG_SYS_HID0_FINAL at h
+ ori r3, r3, (CFG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
SYNC
mtspr HID0, r3
- lis r3, CONFIG_SYS_HID2 at h
- ori r3, r3, CONFIG_SYS_HID2 at l
+ lis r3, CFG_SYS_HID2 at h
+ ori r3, r3, CFG_SYS_HID2 at l
SYNC
mtspr HID2, r3
@@ -550,131 +550,131 @@ setup_bats:
addis r0, r0, 0x0000
/* IBAT 0 */
- addis r4, r0, CONFIG_SYS_IBAT0L at h
- ori r4, r4, CONFIG_SYS_IBAT0L at l
- addis r3, r0, CONFIG_SYS_IBAT0U at h
- ori r3, r3, CONFIG_SYS_IBAT0U at l
+ addis r4, r0, CFG_SYS_IBAT0L at h
+ ori r4, r4, CFG_SYS_IBAT0L at l
+ addis r3, r0, CFG_SYS_IBAT0U at h
+ ori r3, r3, CFG_SYS_IBAT0U at l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
- addis r4, r0, CONFIG_SYS_DBAT0L at h
- ori r4, r4, CONFIG_SYS_DBAT0L at l
- addis r3, r0, CONFIG_SYS_DBAT0U at h
- ori r3, r3, CONFIG_SYS_DBAT0U at l
+ addis r4, r0, CFG_SYS_DBAT0L at h
+ ori r4, r4, CFG_SYS_DBAT0L at l
+ addis r3, r0, CFG_SYS_DBAT0U at h
+ ori r3, r3, CFG_SYS_DBAT0U at l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
- addis r4, r0, CONFIG_SYS_IBAT1L at h
- ori r4, r4, CONFIG_SYS_IBAT1L at l
- addis r3, r0, CONFIG_SYS_IBAT1U at h
- ori r3, r3, CONFIG_SYS_IBAT1U at l
+ addis r4, r0, CFG_SYS_IBAT1L at h
+ ori r4, r4, CFG_SYS_IBAT1L at l
+ addis r3, r0, CFG_SYS_IBAT1U at h
+ ori r3, r3, CFG_SYS_IBAT1U at l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
- addis r4, r0, CONFIG_SYS_DBAT1L at h
- ori r4, r4, CONFIG_SYS_DBAT1L at l
- addis r3, r0, CONFIG_SYS_DBAT1U at h
- ori r3, r3, CONFIG_SYS_DBAT1U at l
+ addis r4, r0, CFG_SYS_DBAT1L at h
+ ori r4, r4, CFG_SYS_DBAT1L at l
+ addis r3, r0, CFG_SYS_DBAT1U at h
+ ori r3, r3, CFG_SYS_DBAT1U at l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
- addis r4, r0, CONFIG_SYS_IBAT2L at h
- ori r4, r4, CONFIG_SYS_IBAT2L at l
- addis r3, r0, CONFIG_SYS_IBAT2U at h
- ori r3, r3, CONFIG_SYS_IBAT2U at l
+ addis r4, r0, CFG_SYS_IBAT2L at h
+ ori r4, r4, CFG_SYS_IBAT2L at l
+ addis r3, r0, CFG_SYS_IBAT2U at h
+ ori r3, r3, CFG_SYS_IBAT2U at l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
- addis r4, r0, CONFIG_SYS_DBAT2L at h
- ori r4, r4, CONFIG_SYS_DBAT2L at l
- addis r3, r0, CONFIG_SYS_DBAT2U at h
- ori r3, r3, CONFIG_SYS_DBAT2U at l
+ addis r4, r0, CFG_SYS_DBAT2L at h
+ ori r4, r4, CFG_SYS_DBAT2L at l
+ addis r3, r0, CFG_SYS_DBAT2U at h
+ ori r3, r3, CFG_SYS_DBAT2U at l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
- addis r4, r0, CONFIG_SYS_IBAT3L at h
- ori r4, r4, CONFIG_SYS_IBAT3L at l
- addis r3, r0, CONFIG_SYS_IBAT3U at h
- ori r3, r3, CONFIG_SYS_IBAT3U at l
+ addis r4, r0, CFG_SYS_IBAT3L at h
+ ori r4, r4, CFG_SYS_IBAT3L at l
+ addis r3, r0, CFG_SYS_IBAT3U at h
+ ori r3, r3, CFG_SYS_IBAT3U at l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
- addis r4, r0, CONFIG_SYS_DBAT3L at h
- ori r4, r4, CONFIG_SYS_DBAT3L at l
- addis r3, r0, CONFIG_SYS_DBAT3U at h
- ori r3, r3, CONFIG_SYS_DBAT3U at l
+ addis r4, r0, CFG_SYS_DBAT3L at h
+ ori r4, r4, CFG_SYS_DBAT3L at l
+ addis r3, r0, CFG_SYS_DBAT3U at h
+ ori r3, r3, CFG_SYS_DBAT3U at l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
- addis r4, r0, CONFIG_SYS_IBAT4L at h
- ori r4, r4, CONFIG_SYS_IBAT4L at l
- addis r3, r0, CONFIG_SYS_IBAT4U at h
- ori r3, r3, CONFIG_SYS_IBAT4U at l
+ addis r4, r0, CFG_SYS_IBAT4L at h
+ ori r4, r4, CFG_SYS_IBAT4L at l
+ addis r3, r0, CFG_SYS_IBAT4U at h
+ ori r3, r3, CFG_SYS_IBAT4U at l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
- addis r4, r0, CONFIG_SYS_DBAT4L at h
- ori r4, r4, CONFIG_SYS_DBAT4L at l
- addis r3, r0, CONFIG_SYS_DBAT4U at h
- ori r3, r3, CONFIG_SYS_DBAT4U at l
+ addis r4, r0, CFG_SYS_DBAT4L at h
+ ori r4, r4, CFG_SYS_DBAT4L at l
+ addis r3, r0, CFG_SYS_DBAT4U at h
+ ori r3, r3, CFG_SYS_DBAT4U at l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
- addis r4, r0, CONFIG_SYS_IBAT5L at h
- ori r4, r4, CONFIG_SYS_IBAT5L at l
- addis r3, r0, CONFIG_SYS_IBAT5U at h
- ori r3, r3, CONFIG_SYS_IBAT5U at l
+ addis r4, r0, CFG_SYS_IBAT5L at h
+ ori r4, r4, CFG_SYS_IBAT5L at l
+ addis r3, r0, CFG_SYS_IBAT5U at h
+ ori r3, r3, CFG_SYS_IBAT5U at l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
- addis r4, r0, CONFIG_SYS_DBAT5L at h
- ori r4, r4, CONFIG_SYS_DBAT5L at l
- addis r3, r0, CONFIG_SYS_DBAT5U at h
- ori r3, r3, CONFIG_SYS_DBAT5U at l
+ addis r4, r0, CFG_SYS_DBAT5L at h
+ ori r4, r4, CFG_SYS_DBAT5L at l
+ addis r3, r0, CFG_SYS_DBAT5U at h
+ ori r3, r3, CFG_SYS_DBAT5U at l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
- addis r4, r0, CONFIG_SYS_IBAT6L at h
- ori r4, r4, CONFIG_SYS_IBAT6L at l
- addis r3, r0, CONFIG_SYS_IBAT6U at h
- ori r3, r3, CONFIG_SYS_IBAT6U at l
+ addis r4, r0, CFG_SYS_IBAT6L at h
+ ori r4, r4, CFG_SYS_IBAT6L at l
+ addis r3, r0, CFG_SYS_IBAT6U at h
+ ori r3, r3, CFG_SYS_IBAT6U at l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
- addis r4, r0, CONFIG_SYS_DBAT6L at h
- ori r4, r4, CONFIG_SYS_DBAT6L at l
- addis r3, r0, CONFIG_SYS_DBAT6U at h
- ori r3, r3, CONFIG_SYS_DBAT6U at l
+ addis r4, r0, CFG_SYS_DBAT6L at h
+ ori r4, r4, CFG_SYS_DBAT6L at l
+ addis r3, r0, CFG_SYS_DBAT6U at h
+ ori r3, r3, CFG_SYS_DBAT6U at l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
- addis r4, r0, CONFIG_SYS_IBAT7L at h
- ori r4, r4, CONFIG_SYS_IBAT7L at l
- addis r3, r0, CONFIG_SYS_IBAT7U at h
- ori r3, r3, CONFIG_SYS_IBAT7U at l
+ addis r4, r0, CFG_SYS_IBAT7L at h
+ ori r4, r4, CFG_SYS_IBAT7L at l
+ addis r3, r0, CFG_SYS_IBAT7U at h
+ ori r3, r3, CFG_SYS_IBAT7U at l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
- addis r4, r0, CONFIG_SYS_DBAT7L at h
- ori r4, r4, CONFIG_SYS_DBAT7L at l
- addis r3, r0, CONFIG_SYS_DBAT7U at h
- ori r3, r3, CONFIG_SYS_DBAT7U at l
+ addis r4, r0, CFG_SYS_DBAT7L at h
+ ori r4, r4, CFG_SYS_DBAT7L at l
+ addis r3, r0, CFG_SYS_DBAT7U at h
+ ori r3, r3, CFG_SYS_DBAT7U at l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
#endif
@@ -1095,7 +1095,7 @@ unlock_ram_in_cache:
#endif /* !MINIMAL_SPL */
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
-#ifdef CONFIG_SYS_FLASHBOOT
+#ifdef CFG_SYS_FLASHBOOT
map_flash_by_law1:
/* When booting from ROM (Flash or EPROM), clear the */
/* Address Mask in OR0 so ROM appears everywhere */
@@ -1182,4 +1182,4 @@ remap_flash_by_law0:
twi 0,r4,0
isync
blr
-#endif /* CONFIG_SYS_FLASHBOOT */
+#endif /* CFG_SYS_FLASHBOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f07e8ab388e8..96183ac2c84b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -73,11 +73,11 @@ void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
get_sys_info(&sysinfo);
if (sysinfo.diff_sysclk == 1) {
clrbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ CFG_SYS_FSL_USB_PLLPRG2_MFI);
setbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
- CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+ CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+ CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
}
}
#endif
@@ -89,18 +89,18 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
/* Increase Disconnect Threshold by 50mV */
- xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
INC_DCNT_THRESHOLD_50MV;
/* Enable programming of USB High speed Disconnect threshold */
- xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
/* Increase Disconnect Threshold by 50mV */
- xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
INC_DCNT_THRESHOLD_50MV;
/* Enable programming of USB High speed Disconnect threshold */
- xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
#else
@@ -108,22 +108,22 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
u32 status = in_be32(&usb_phy->status1);
u32 squelch_prog_rd_0_2 =
- (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
- & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+ (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+ & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
u32 squelch_prog_rd_3_5 =
- (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
- & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+ (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+ & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
setbits_be32(&usb_phy->config1,
- CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+ CFG_SYS_FSL_USB_HS_DISCNCT_INC);
setbits_be32(&usb_phy->config2,
- CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+ CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
- temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+ temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
- temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+ temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
#endif
}
@@ -827,7 +827,7 @@ int cpu_init_r(void)
fsl_erratum_a006261_workaround(usb_phy1);
#endif
out_be32(&usb_phy1->usb_enable_override,
- CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+ CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
#endif
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
@@ -839,7 +839,7 @@ int cpu_init_r(void)
fsl_erratum_a006261_workaround(usb_phy2);
#endif
out_be32(&usb_phy2->usb_enable_override,
- CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+ CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
#endif
@@ -861,25 +861,25 @@ int cpu_init_r(void)
struct ccsr_usb_phy __iomem *usb_phy =
(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
setbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
- CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
- CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+ CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+ CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+ CFG_SYS_FSL_USB_PLLPRG2_MFI |
+ CFG_SYS_FSL_USB_PLLPRG2_PLL_EN);
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
usb_single_source_clk_configure(usb_phy);
#endif
setbits_be32(&usb_phy->port1.ctrl,
- CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ CFG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port1.drvvbuscfg,
- CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(&usb_phy->port1.pwrfltcfg,
- CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+ CFG_SYS_FSL_USB_PWRFLT_CR_EN);
setbits_be32(&usb_phy->port2.ctrl,
- CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ CFG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port2.drvvbuscfg,
- CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(&usb_phy->port2.pwrfltcfg,
- CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+ CFG_SYS_FSL_USB_PWRFLT_CR_EN);
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 35142508c30e..e26436bf5701 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
int nodeoff;
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
+#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
@@ -554,7 +554,7 @@ void fdt_fixup_dma3(void *blob)
case 16:
#endif
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
- CONFIG_SYS_ELO3_DMA3);
+ CFG_SYS_ELO3_DMA3);
if (nodeoff > 0)
fdt_status_disabled(blob, nodeoff);
else
@@ -616,11 +616,11 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_add_enet_stashing(blob);
-#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
-#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#ifndef CFG_FSL_TBCLK_EXTRA_DIV
+#define CFG_FSL_TBCLK_EXTRA_DIV 1
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+ "timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV,
1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 18790921dd72..4b8844a4d960 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -255,14 +255,14 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
}
#endif
-#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CFG_SYS_MAX_PCI_EPS 8
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
int ep_liodn_start)
{
int off, pci_idx = 0, pci_cnt = 0, i, rc;
const uint32_t *base_liodn;
- uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+ uint32_t liodn_offs[CFG_SYS_MAX_PCI_EPS + 1] = { 0 };
/*
* Count the number of pci nodes.
@@ -282,7 +282,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
path, fdt_strerror(rc));
continue;
}
- for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ for (i = 0; i < CFG_SYS_MAX_PCI_EPS; i++)
liodn_offs[i + 1] = ep_liodn_start +
i * pci_cnt + pci_idx - *base_liodn;
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 1c051d18980f..8e1f6c964d3f 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -240,8 +240,8 @@ int pamu_init(void)
spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
/* Allocate space for Primary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR))
- ppaact = (void *)CONFIG_SPL_PPAACT_ADDR;
+#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR))
+ ppaact = (void *)CFG_SPL_PPAACT_ADDR;
#else
ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
if (!ppaact)
@@ -250,8 +250,8 @@ int pamu_init(void)
memset(ppaact, 0, ppaact_size);
/* Allocate space for Secondary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR))
- sec = (void *)CONFIG_SPL_SPAACT_ADDR;
+#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR))
+ sec = (void *)CFG_SPL_SPAACT_ADDR;
#else
sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
if (!sec)
@@ -266,7 +266,7 @@ int pamu_init(void)
spaact_lim = spaact_phys + spaact_size;
/* Configure all PAMU's */
- for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ for (i = 0; i < CFG_NUM_PAMU; i++) {
regs = (struct ccsr_pamu *)base_addr;
out_be32(®s->ppbah, ppaact_phys >> 32);
@@ -293,7 +293,7 @@ void pamu_enable(void)
{
u32 i = 0;
u32 base_addr = CFG_SYS_PAMU_ADDR;
- for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ for (i = 0; i < CFG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
sync();
@@ -307,7 +307,7 @@ void pamu_reset(void)
u32 base_addr = CFG_SYS_PAMU_ADDR;
struct ccsr_pamu *regs;
- for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ for (i = 0; i < CFG_NUM_PAMU; i++) {
regs = (struct ccsr_pamu *)base_addr;
/* Clear PPAACT Base register */
out_be32(®s->ppbah, 0);
@@ -331,7 +331,7 @@ void pamu_disable(void)
u32 base_addr = CFG_SYS_PAMU_ADDR;
- for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ for (i = 0; i < CFG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
sync();
base_addr += PAMU_OFFSET;
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
index 07e822b796ed..d0d33fd16363 100644
--- a/arch/powerpc/include/asm/fsl_pamu.h
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -6,7 +6,7 @@
#ifndef __PAMU_H
#define __PAMU_H
-#define CONFIG_NUM_PAMU 16
+#define CFG_NUM_PAMU 16
#define NUM_PPAACT_ENTRIES 512
#define NUM_SPAACT_ENTRIES 256
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 236098e718ef..221f9d842a83 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -41,10 +41,10 @@
* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
* due to space crunch on CPC and thus malloc will not work.
*/
-#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
-#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
-#define CONFIG_SPL_JR0_LIODN_S 454
-#define CONFIG_SPL_JR0_LIODN_NS 458
+#define CFG_SPL_PPAACT_ADDR 0x2e000000
+#define CFG_SPL_SPAACT_ADDR 0x2f000000
+#define CFG_SPL_JR0_LIODN_S 454
+#define CFG_SPL_JR0_LIODN_NS 458
#endif /* ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 1df0822e9d73..7b392b06bcba 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -41,8 +41,8 @@ static ulong get_sp (void);
extern void ft_fixup_num_cores(void *blob);
static void set_clocks_in_mhz (struct bd_info *kbd);
-#ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
-#define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
+#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE
+#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
#endif
static void boot_jump_linux(struct bootm_headers *images)
@@ -133,7 +133,7 @@ void arch_lmb_reserve(struct lmb *lmb)
#endif
size = min(bootm_size, get_effective_memsize());
- size = min(size, (ulong)CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
+ size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE);
if (size < bootm_size) {
ulong base = bootmap_base + size;
diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c
index bdb8030c27f0..df312dfa28ef 100644
--- a/arch/powerpc/lib/interrupts.c
+++ b/arch/powerpc/lib/interrupts.c
@@ -17,8 +17,8 @@
#include <asm/ptrace.h>
#ifndef CONFIG_MPC83XX_TIMER
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#ifndef CFG_SYS_WATCHDOG_FREQ
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
@@ -80,7 +80,7 @@ void timer_interrupt(struct pt_regs *regs)
timestamp++;
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
- if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
+ if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0)
schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index edafad36b38d..56c5da86e867 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -93,7 +93,7 @@
#define DEFAULT_RSTVEC 0x00001000
#define DEFAULT_NMIVEC 0x00001004
#define DEFAULT_MTVEC 0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
+#define CFG_STRING_ADDR 0x0000100C
#define EXT_IO_BASE 0x40000000
#define DRAM_BASE 0x80000000
diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl
index 2a0fd33265d5..4fb13f34d425 100644
--- a/arch/x86/include/asm/acpi/chromeos.asl
+++ b/arch/x86/include/asm/acpi/chromeos.asl
@@ -5,7 +5,7 @@
#ifdef CONFIG_CHROMEOS
-#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+#define CFG_VBOOT_VBNV_OFFSET 0x26
#include <asm/acpi/vbnv_layout.h>
@@ -68,7 +68,7 @@ Device (CRHW)
Name(VNBV, Package() {
// See src/vendorcode/google/chromeos/Kconfig
// for the definition of these:
- CONFIG_VBOOT_VBNV_OFFSET,
+ CFG_VBOOT_VBNV_OFFSET,
VBOOT_VBNV_BLOCK_SIZE
})
Return(VNBV)
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index 0cfb7c522f67..80ad62c2c665 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -26,8 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
-#define CONFIG_NVS_LOCATION 0xf4800000
-#define CONFIG_NVS_SIZE (512 << 10)
+#define CFG_NVS_LOCATION 0xf4800000
+#define CFG_NVS_SIZE (512 << 10)
static struct serdes_map board_serdes_map[] = {
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
@@ -109,7 +109,7 @@ int board_init(void)
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/* window for NVS */
- mbus_dt_setup_win(CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+ mbus_dt_setup_win(CFG_NVS_LOCATION, CFG_NVS_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 99fb67ecedc2..ee65a596838a 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -220,7 +220,7 @@ int board_eth_init(struct bd_info *bis)
int rc = 0;
#ifndef CONFIG_DM_ETH
#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ rc = smc911x_initialize(0, CFG_SMC911X_BASE);
#endif
#endif
return rc;
diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
index 4dbd847d42a1..90cc33a6e460 100644
--- a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
+++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
@@ -12,7 +12,7 @@
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51
+#define CFG_SYS_I2C_EEPROM_ADDR_P1 0x51
static iomux_v3_cfg_t const eeprom_pads[] = {
IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -40,7 +40,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len)
struct udevice *dev;
int ret;
- ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+ ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
if (ret) {
printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
@@ -57,7 +57,7 @@ static int cl_eeprom_write(uint offset, uchar *buf, int len)
cl_eeprom_we(1);
- ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1,
+ ret = i2c_get_chip_for_busnum(1, CFG_SYS_I2C_EEPROM_ADDR_P1,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
if (ret) {
printf("%s: Cannot find EEPROM: %d\n", __func__, ret);
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index e3a0f266a4c5..474dca72929f 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -226,8 +226,8 @@ const struct lpsc_resource lpsc[] = {
const int lpsc_size = ARRAY_SIZE(lpsc);
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
+#define CFG_DA850_EVM_MAX_CPU_CLK 300000000
#endif
#define REV_AM18X_EVM 0x100
@@ -245,7 +245,7 @@ const int lpsc_size = ARRAY_SIZE(lpsc);
u32 get_board_rev(void)
{
char *s;
- u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+ u32 maxcpuclk = CFG_DA850_EVM_MAX_CPU_CLK;
u32 rev = 0;
s = env_get("maxcpuclk");
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index cd021cc8e583..5ffd420fff36 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -139,8 +139,8 @@ const struct lpsc_resource lpsc[] = {
const int lpsc_size = ARRAY_SIZE(lpsc);
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
+#ifndef CFG_DA850_EVM_MAX_CPU_CLK
+#define CFG_DA850_EVM_MAX_CPU_CLK 456000000
#endif
int board_early_init_f(void)
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 648d77fd21e3..de224d4d2834 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -62,8 +62,8 @@ DECLARE_GLOBAL_DATA_PTR;
* To get the boot device from 'am33xx_spl_board_init' to
* 'board_late_init' we therefore use a scratch register from the RTC.
*/
-#define CONFIG_SYS_RTC_SCRATCH0 0x60
-#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+#define CFG_SYS_RTC_SCRATCH0 0x60
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0)
#ifdef CONFIG_SPL_BUILD
static void save_boot_device(void)
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 8f3fb5fa81b2..e7e07fff86c3 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -10,8 +10,8 @@
/*
* CADMUS Board System Registers
*/
-#ifndef CONFIG_SYS_CADMUS_BASE_REG
-#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
+#ifndef CFG_SYS_CADMUS_BASE_REG
+#define CFG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
#endif
typedef struct cadmus_reg {
@@ -30,7 +30,7 @@ typedef struct cadmus_reg {
unsigned int
get_board_version(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
return cadmus->cm_ver;
}
@@ -39,7 +39,7 @@ get_board_version(void)
unsigned long
get_board_sys_clk(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
@@ -57,7 +57,7 @@ get_board_sys_clk(void)
unsigned int
get_pci_slot(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
/*
* PCI slot in USER bits CSR[6:7] by convention.
@@ -69,7 +69,7 @@ get_pci_slot(void)
unsigned int
get_pci_dual(void)
{
- volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG;
/*
* PCI DUAL in CM_PCI[3]
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 029d06bbf9d6..b47ce052516e 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -28,9 +28,9 @@
#endif
#if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
+#define CFG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#else
-#define CONFIG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR
+#define CFG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR
#endif
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
@@ -44,7 +44,7 @@ int fsl_check_boot_mode_secure(void)
{
uint32_t val;
struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR);
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_DCFG_ADDR);
val = sfp_in32(&sfp_regs->ospr) & ITS_MASK;
if (val == ITS_MASK)
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index cb9f4549725c..7096b107e540 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -149,8 +149,8 @@ static int set_px_corepll(unsigned long corepll)
return 1;
}
-#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
-#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
+#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CFG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
#endif
/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
@@ -159,7 +159,7 @@ static int set_px_corepll(unsigned long corepll)
* or various other PIXIS registers to determine the values for COREPLL,
* MPXPLL, and SYSCLK.
*
- * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
* register that tells the pixis to use the various PIXIS register.
*/
static void read_from_px_regs(int set)
@@ -167,18 +167,18 @@ static void read_from_px_regs(int set)
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
- tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+ tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE;
else
- tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+ tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
-/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
*/
-#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
-#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
+#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE
+#define CFG_SYS_PIXIS_VBOOT_ENABLE 0x04
#endif
/* Configure the source of the boot location
@@ -194,14 +194,14 @@ static void read_from_px_regs_altbank(int set)
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
- tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+ tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE;
else
- tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+ tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
-/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
* tells the PIXIS what the alternate flash bank is.
*
* Note that it's not really a mask. It contains the actual LBMAP bits that
@@ -209,8 +209,8 @@ static void read_from_px_regs_altbank(int set)
* primary bank has these bits set to 0, and the alternate bank has these
* bits set to 1.
*/
-#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
-#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
+#ifndef CFG_SYS_PIXIS_VBOOT_MASK
+#define CFG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
/* Tell the PIXIS to boot from the default flash bank
@@ -220,7 +220,7 @@ static void read_from_px_regs_altbank(int set)
*/
static void clear_altbank(void)
{
- clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+ clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
}
/* Tell the PIXIS to boot from the alternate flash bank
@@ -230,7 +230,7 @@ static void clear_altbank(void)
*/
static void set_altbank(void)
{
- setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+ setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK);
}
/* Reset the board with watchdog disabled.
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 645c56c73d53..cd1f83e3d068 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -314,7 +314,7 @@ int board_eth_init(struct bd_info *bis)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -322,7 +322,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index 3cae2a08677c..cc95214c4e3f 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -28,7 +28,7 @@ int board_eth_init(struct bd_info *bis)
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -36,7 +36,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
index 71c4c21cd4fd..d1a2bfe18855 100644
--- a/board/freescale/ls1046afrwy/eth.c
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -27,7 +27,7 @@ int board_eth_init(struct bd_info *bis)
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 926bd74ddc67..bbf8b8c2bee5 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -285,7 +285,7 @@ int board_eth_init(struct bd_info *bis)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index af70d1077344..bbc22a3cdf4a 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis)
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -37,7 +37,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 3e12c816abc4..c0d05539c5c0 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -139,14 +139,14 @@ int board_eth_init(struct bd_info *bis)
initialize_lane_to_slot();
dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index ed6b36339f74..ad78f72f98c8 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -41,7 +41,7 @@ int board_eth_init(struct bd_info *bis)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 3906c8381e01..5eca9386f6eb 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -26,7 +26,7 @@ int board_eth_init(struct bd_info *bis)
printf("Initializing Fman\n");
memac_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 62261f50ea94..569b193eab78 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -474,7 +474,7 @@ int board_eth_init(struct bd_info *bis)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -482,7 +482,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 241ee5a4a253..2e52543847bf 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -54,7 +54,7 @@ int board_eth_init(struct bd_info *bis)
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
@@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis)
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index 559192e9001e..86992829caf4 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -58,7 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
-#define CONFIG_SMC911X_BASE 0x08000000
+#define CFG_SMC911X_BASE 0x08000000
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
@@ -226,7 +226,7 @@ int board_late_init(void)
#ifdef CONFIG_SMC911X
enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
- CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+ CFG_SMC911X_BASE, GPMC_SIZE_16M);
#endif
return 0;
}
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index ea090575fb20..8e1ae29e2219 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -327,7 +327,7 @@ int board_eth_init(struct bd_info *bis)
struct eth_device *dev;
uchar eth_addr[6];
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ rc = smc911x_initialize(0, CFG_SMC911X_BASE);
if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
dev = eth_get_dev_by_index(0);
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 429f886771b7..086421d9265d 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -109,7 +109,7 @@ int dram_init(void)
}
static struct coldfire_serial_plat mcf5307_serial_plat = {
- .base = CONFIG_SYS_UART_BASE,
+ .base = CFG_SYS_UART_BASE,
.port = 0,
.baudrate = CONFIG_BAUDRATE,
};
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index a7f9a7eca167..a4d6a0138d9b 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -33,7 +33,7 @@
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
-#define CONFIG_SMC911X_BASE 0x2C000000
+#define CFG_SMC911X_BASE 0x2C000000
DECLARE_GLOBAL_DATA_PTR;
@@ -54,7 +54,7 @@ static void omap3_evm_get_revision(void)
unsigned int smsc_id;
/* Ethernet PHY ID is stored at ID_REV register */
- smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+ smsc_id = readl(CFG_SMC911X_BASE + 0x50) & 0xFFFF0000;
printf("Read back SMSC id 0x%x\n", smsc_id);
switch (smsc_id) {
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 1c40fd27a054..60ed2c9f6f9e 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -27,9 +27,9 @@
#include <asm/cache.h>
#include <asm/io.h>
-#ifndef CONFIG_SYS_XIMG_LEN
+#ifndef CFG_SYS_XIMG_LEN
/* use 8MByte as default max gunzip size */
-#define CONFIG_SYS_XIMG_LEN 0x800000
+#define CFG_SYS_XIMG_LEN 0x800000
#endif
static int
@@ -52,7 +52,7 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
size_t fit_len;
#endif
#ifdef CONFIG_GZIP
- uint unc_len = CONFIG_SYS_XIMG_LEN;
+ uint unc_len = CFG_SYS_XIMG_LEN;
#endif
uint8_t comp;
diff --git a/common/command.c b/common/command.c
index 41c91c6d8c87..b2799eaa034b 100644
--- a/common/command.c
+++ b/common/command.c
@@ -66,7 +66,7 @@ int _do_help(struct cmd_tbl *cmd_start, int cmd_items, struct cmd_tbl *cmdtp,
return 1;
if (usage == NULL)
continue;
- printf("%-*s- %s\n", CONFIG_SYS_HELP_CMD_WIDTH,
+ printf("%-*s- %s\n", CFG_SYS_HELP_CMD_WIDTH,
cmd_array[i]->name, usage);
}
return 0;
diff --git a/doc/README.davinci b/doc/README.davinci
index 326efa0a2d6d..f368f99a41e2 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -58,7 +58,7 @@ Please make sure you understand the restrictions placed on this clock in the
device specific datasheet before setting up this variable. This information is
passed to the Linux kernel using the ATAG_REVISION atag.
-If "maxcpuclk" is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK
+If "maxcpuclk" is not defined, the configuration CFG_DA850_EVM_MAX_CPU_CLK
is used to obtain this information.
Links
diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc
index 2ccd4288d281..a33f4a75742a 100644
--- a/doc/README.fec_mxc
+++ b/doc/README.fec_mxc
@@ -7,7 +7,7 @@ CONFIG_FEC_MXC
CONFIG_MII
Must be defined if CONFIG_FEC_MXC is defined.
-CONFIG_FEC_MXC_SWAP_PACKET
+CFG_FEC_MXC_SWAP_PACKET
Forced on iff MX28.
Swaps the bytes order of all words(4 byte units) in the packet.
This should not be specified by a board file. It is cpu specific.
diff --git a/doc/develop/environment.rst b/doc/develop/environment.rst
index 0b86fafbff7e..e1783462bb02 100644
--- a/doc/develop/environment.rst
+++ b/doc/develop/environment.rst
@@ -18,7 +18,7 @@ The callbacks are named and associated with a function using the
U_BOOT_ENV_CALLBACK macro in your board or driver code.
These callbacks are associated with variables in one of two ways. The
-static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+static list can be added to by defining CFG_ENV_CALLBACK_LIST_STATIC
in the board configuration to a string that defines a list of
associations. The list must be in the following format::
diff --git a/doc/usage/netconsole.rst b/doc/usage/netconsole.rst
index 0156f0212d99..2aa3b9ccc59b 100644
--- a/doc/usage/netconsole.rst
+++ b/doc/usage/netconsole.rst
@@ -9,7 +9,7 @@ set either of these variables to "nc". Input and output can be
switched independently.
The default buffer size can be overridden by setting
-CONFIG_NETCONSOLE_BUFFER_SIZE.
+CFG_NETCONSOLE_BUFFER_SIZE.
We use an environment variable 'ncip' to set the IP address and the
port of the destination. The format is <ip_addr>:<port>. If <port> is
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index ee822edd6c8e..ceb66dd6270d 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -328,7 +328,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
caam = &caam_st;
#endif
unsigned long long timeval = 0;
- unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
+ unsigned long long timeout = CFG_USEC_DEQ_TIMEOUT;
struct result op;
int ret = 0;
@@ -743,8 +743,8 @@ int sec_init_idx(uint8_t sec_idx)
* creating PAMU entries corresponding to these.
* For normal build, these are set in set_liodns().
*/
- liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
- liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
+ liodn_ns = CFG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
+ liodn_s = CFG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
~(JRNSLIODN_MASK | JRSLIODN_MASK);
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 3eb7be79da41..4e4c4af5805f 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -15,7 +15,7 @@
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
-#define CONFIG_USEC_DEQ_TIMEOUT 10000000U
+#define CFG_USEC_DEQ_TIMEOUT 10000000U
#define DEFAULT_JR_ID 0
#define DEFAULT_JR_LIODN 0
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 759921bc5824..8f8c2c864c3f 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -822,7 +822,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
twot_en = popts->twot_en;
}
- sdram_type = CONFIG_FSL_SDRAM_TYPE;
+ sdram_type = CFG_FSL_SDRAM_TYPE;
dyn_pwr = popts->dynamic_power;
dbw = popts->data_bus_width;
@@ -926,7 +926,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
rcw_en = 1;
/* DDR4 can have address parity for UDIMM and discrete */
- if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
+ if ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
(!popts->registered_dimm_en)) {
ap_en = 0;
} else {
@@ -1188,7 +1188,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
* handled by register chip and RCW settings.
*/
if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
- ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
+ ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
!popts->registered_dimm_en)) {
if (mclk_ps >= 935) {
/* for DDR4-1600/1866/2133 */
@@ -1223,7 +1223,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
}
if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
- ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
+ ((CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
!popts->registered_dimm_en)) {
if (mclk_ps >= 935) {
/* for DDR4-1600/1866/2133 */
@@ -1983,7 +1983,7 @@ static void set_timing_cfg_7(const unsigned int ctrl_num,
tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
- CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
+ CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
/* for DDR4 only */
par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 9555b9a29d45..7cff82345847 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -753,7 +753,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
defined(CONFIG_SYS_FSL_DDR4)
const struct dynamic_odt *pdodt = odt_unknown;
#endif
-#if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
+#if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
ulong ddr_freq;
#endif
@@ -1024,7 +1024,7 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
if (popts->registered_dimm_en ||
- (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
+ (CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
popts->ap_en = 1;
}
}
@@ -1302,7 +1302,7 @@ done:
popts->package_3ds = pdimm->package_3ds;
-#if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
+#if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
if (popts->registered_dimm_en) {
popts->rcw_override = 1;
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index fc99a5f48314..3ded27f9b3ff 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -34,8 +34,8 @@
/*
* Check for errors during configuration by default
*/
-#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
-#define CONFIG_SYS_FPGA_CHECK_ERROR
+#ifndef CFG_SYS_FPGA_CHECK_ERROR
+#define CFG_SYS_FPGA_CHECK_ERROR
#endif
/*
@@ -323,7 +323,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
@@ -458,7 +458,7 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
break;
}
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 53dd780a6ca2..a2e3b305fa41 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -40,8 +40,8 @@
#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
-#ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
+#ifndef CFG_SYS_FPGA_PROG_TIME
+#define CFG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
#define DUMMY_WORD 0xffffffff
@@ -181,7 +181,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
return FPGA_FAIL;
}
- if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+ if (get_timer(ts) > CFG_SYS_FPGA_PROG_TIME) {
printf("%s: Timeout wait for DMA to complete\n",
__func__);
return FPGA_FAIL;
diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c
index 276a3b350dc2..bf693c8d4578 100644
--- a/drivers/gpio/mpc83xx_gpio.c
+++ b/drivers/gpio/mpc83xx_gpio.c
@@ -9,23 +9,23 @@
#include <asm/gpio.h>
#include <asm/io.h>
-#ifndef CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION
-#define CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION 0
+#ifndef CFG_MPC83XX_GPIO_0_INIT_DIRECTION
+#define CFG_MPC83XX_GPIO_0_INIT_DIRECTION 0
#endif
-#ifndef CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION
-#define CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION 0
+#ifndef CFG_MPC83XX_GPIO_1_INIT_DIRECTION
+#define CFG_MPC83XX_GPIO_1_INIT_DIRECTION 0
#endif
-#ifndef CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
-#define CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0
+#ifndef CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN
+#define CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0
#endif
-#ifndef CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
-#define CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0
+#ifndef CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN
+#define CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0
#endif
-#ifndef CONFIG_MPC83XX_GPIO_0_INIT_VALUE
-#define CONFIG_MPC83XX_GPIO_0_INIT_VALUE 0
+#ifndef CFG_MPC83XX_GPIO_0_INIT_VALUE
+#define CFG_MPC83XX_GPIO_0_INIT_VALUE 0
#endif
-#ifndef CONFIG_MPC83XX_GPIO_1_INIT_VALUE
-#define CONFIG_MPC83XX_GPIO_1_INIT_VALUE 0
+#ifndef CFG_MPC83XX_GPIO_1_INIT_VALUE
+#define CFG_MPC83XX_GPIO_1_INIT_VALUE 0
#endif
static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS];
@@ -152,18 +152,18 @@ void mpc83xx_gpio_init_f(void)
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
#if MPC83XX_GPIO_CTRLRS >= 1
- out_be32(&im->gpio[0].dir, CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION);
- out_be32(&im->gpio[0].odr, CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN);
- out_be32(&im->gpio[0].dat, CONFIG_MPC83XX_GPIO_0_INIT_VALUE);
+ out_be32(&im->gpio[0].dir, CFG_MPC83XX_GPIO_0_INIT_DIRECTION);
+ out_be32(&im->gpio[0].odr, CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN);
+ out_be32(&im->gpio[0].dat, CFG_MPC83XX_GPIO_0_INIT_VALUE);
out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */
out_be32(&im->gpio[0].imr, 0);
out_be32(&im->gpio[0].icr, 0);
#endif
#if MPC83XX_GPIO_CTRLRS >= 2
- out_be32(&im->gpio[1].dir, CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION);
- out_be32(&im->gpio[1].odr, CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN);
- out_be32(&im->gpio[1].dat, CONFIG_MPC83XX_GPIO_1_INIT_VALUE);
+ out_be32(&im->gpio[1].dir, CFG_MPC83XX_GPIO_1_INIT_DIRECTION);
+ out_be32(&im->gpio[1].odr, CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN);
+ out_be32(&im->gpio[1].dat, CFG_MPC83XX_GPIO_1_INIT_VALUE);
out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */
out_be32(&im->gpio[1].imr, 0);
out_be32(&im->gpio[1].icr, 0);
@@ -174,10 +174,10 @@ void mpc83xx_gpio_init_f(void)
void mpc83xx_gpio_init_r(void)
{
#if MPC83XX_GPIO_CTRLRS >= 1
- gpio_output_value[0] = CONFIG_MPC83XX_GPIO_0_INIT_VALUE;
+ gpio_output_value[0] = CFG_MPC83XX_GPIO_0_INIT_VALUE;
#endif
#if MPC83XX_GPIO_CTRLRS >= 2
- gpio_output_value[1] = CONFIG_MPC83XX_GPIO_1_INIT_VALUE;
+ gpio_output_value[1] = CFG_MPC83XX_GPIO_1_INIT_VALUE;
#endif
}
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 147a4b91f0c5..d312f35f044f 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -23,16 +23,16 @@
* released the bus. If not defined in the board header file, then use a
* generic value.
*/
-#ifndef CONFIG_I2C_MBB_TIMEOUT
-#define CONFIG_I2C_MBB_TIMEOUT 100000
+#ifndef CFG_I2C_MBB_TIMEOUT
+#define CFG_I2C_MBB_TIMEOUT 100000
#endif
/* The maximum number of microseconds we will wait for a read or write
* operation to complete. If not defined in the board header file, then use a
* generic value.
*/
-#ifndef CONFIG_I2C_TIMEOUT
-#define CONFIG_I2C_TIMEOUT 100000
+#ifndef CFG_I2C_TIMEOUT
+#define CFG_I2C_TIMEOUT 100000
#endif
#define I2C_READ_BIT 1
@@ -221,7 +221,7 @@ static uint get_i2c_clock(int bus)
static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
{
- const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT);
unsigned long long timeval = 0;
int ret = -1;
uint flags = 0;
@@ -270,7 +270,7 @@ err:
static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
slaveadd, int i2c_clk, int busnum)
{
- const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT);
unsigned long long timeval;
writeb(0, &base->cr); /* stop I2C controller */
@@ -296,7 +296,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
static int i2c_wait4bus(const struct fsl_i2c_base *base)
{
unsigned long long timeval = get_ticks();
- const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
+ const unsigned long long timeout = usec2ticks(CFG_I2C_MBB_TIMEOUT);
while (readb(&base->sr) & I2C_SR_MBB) {
if ((get_ticks() - timeval) > timeout)
@@ -310,7 +310,7 @@ static int i2c_wait(const struct fsl_i2c_base *base, int write)
{
u32 csr;
unsigned long long timeval = get_ticks();
- const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
+ const unsigned long long timeout = usec2ticks(CFG_I2C_TIMEOUT);
do {
csr = readb(&base->sr);
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
index 774129ad8ea5..496f4feec566 100644
--- a/drivers/i2c/lpc32xx_i2c.c
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -20,12 +20,12 @@
* Provide default speed and slave if target did not
*/
-#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
-#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
+#if !defined(CFG_SYS_I2C_LPC32XX_SPEED)
+#define CFG_SYS_I2C_LPC32XX_SPEED 350000
#endif
-#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
-#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#if !defined(CFG_SYS_I2C_LPC32XX_SLAVE)
+#define CFG_SYS_I2C_LPC32XX_SLAVE 0
#endif
/* TX register fields */
@@ -260,15 +260,15 @@ static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
- CONFIG_SYS_I2C_LPC32XX_SPEED,
- CONFIG_SYS_I2C_LPC32XX_SLAVE,
+ CFG_SYS_I2C_LPC32XX_SPEED,
+ CFG_SYS_I2C_LPC32XX_SLAVE,
0)
U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, lpc32xx_i2c_init, lpc32xx_i2c_probe_chip,
lpc32xx_i2c_read, lpc32xx_i2c_write,
lpc32xx_i2c_set_bus_speed,
- CONFIG_SYS_I2C_LPC32XX_SPEED,
- CONFIG_SYS_I2C_LPC32XX_SLAVE,
+ CFG_SYS_I2C_LPC32XX_SPEED,
+ CFG_SYS_I2C_LPC32XX_SLAVE,
1)
U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 2822749971af..93bbc6916e58 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -205,9 +205,9 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
case 1:
return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE1;
#endif
-#ifdef CONFIG_I2C_MVTWSI_BASE2
+#ifdef CFG_I2C_MVTWSI_BASE2
case 2:
- return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
+ return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE2;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE3
case 3:
@@ -750,7 +750,7 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
#endif
-#ifdef CONFIG_I2C_MVTWSI_BASE2
+#ifdef CFG_I2C_MVTWSI_BASE2
U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
twsi_i2c_read, twsi_i2c_write,
twsi_i2c_set_bus_speed,
diff --git a/drivers/i2c/octeon_i2c.c b/drivers/i2c/octeon_i2c.c
index e54ef18e5155..f2dea5626cbb 100644
--- a/drivers/i2c/octeon_i2c.c
+++ b/drivers/i2c/octeon_i2c.c
@@ -146,7 +146,7 @@ enum {
TWSI_STAT_IDLE = 0xf8
};
-#define CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR 0x77
+#define CFG_SYS_I2C_OCTEON_SLAVE_ADDR 0x77
enum {
PROBE_PCI = 0, /* PCI based probing */
@@ -800,7 +800,7 @@ static int octeon_i2c_probe(struct udevice *dev)
twsi->base += twsi->data->reg_offs;
i2c_slave_addr = dev_read_u32_default(dev, "i2c-sda-hold-time-ns",
- CONFIG_SYS_I2C_OCTEON_SLAVE_ADDR);
+ CFG_SYS_I2C_OCTEON_SLAVE_ADDR);
ret = clk_get_by_index(dev, 0, &twsi->clk);
if (ret < 0)
diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c
index b913069849ac..30679f80cf15 100644
--- a/drivers/misc/gpio_led.c
+++ b/drivers/misc/gpio_led.c
@@ -9,11 +9,11 @@
#include <status_led.h>
#include <asm/gpio.h>
-#ifndef CONFIG_GPIO_LED_INVERTED_TABLE
-#define CONFIG_GPIO_LED_INVERTED_TABLE {}
+#ifndef CFG_GPIO_LED_INVERTED_TABLE
+#define CFG_GPIO_LED_INVERTED_TABLE {}
#endif
-static led_id_t gpio_led_inv[] = CONFIG_GPIO_LED_INVERTED_TABLE;
+static led_id_t gpio_led_inv[] = CFG_GPIO_LED_INVERTED_TABLE;
static int gpio_led_gpio_value(led_id_t mask, int state)
{
diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c
index 84564b2f70a5..dfe73d64e46a 100644
--- a/drivers/mtd/nand/raw/kmeter1_nand.c
+++ b/drivers/mtd/nand/raw/kmeter1_nand.c
@@ -10,13 +10,13 @@
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
-#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
+#define CFG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CFG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
-#define read_mode() in_8(CONFIG_NAND_MODE_REG)
-#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
-#define read_data() in_8(CONFIG_NAND_DATA_REG)
-#define write_data(val) out_8(CONFIG_NAND_DATA_REG, val)
+#define read_mode() in_8(CFG_NAND_MODE_REG)
+#define write_mode(val) out_8(CFG_NAND_MODE_REG, val)
+#define read_data() in_8(CFG_NAND_DATA_REG)
+#define write_data(val) out_8(CFG_NAND_DATA_REG, val)
#define KPN_RDY2 (1 << 7)
#define KPN_RDY1 (1 << 6)
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index dfc35d6eabf0..cdbdbd6ea581 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -11,7 +11,7 @@
#define ESPI_BOOT_IMAGE_SIZE 0x48
#define ESPI_BOOT_IMAGE_ADDR 0x50
-#define CONFIG_CFG_DATA_SECTOR 0
+#define CFG_CFG_DATA_SECTOR 0
void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
{
@@ -62,7 +62,7 @@ void fsl_spi_boot(void)
}
memset(buf, 0, flash->page_size);
- spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR,
+ spi_flash_read(flash, CFG_CFG_DATA_SECTOR,
flash->page_size, (void *)buf);
offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
/* Skip spl code */
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
index a16c998b2ab9..da1f3f458080 100644
--- a/drivers/net/ag7xxx.c
+++ b/drivers/net/ag7xxx.c
@@ -143,11 +143,11 @@ enum ag7xxx_model {
#define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
#define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
-#define CONFIG_TX_DESCR_NUM 8
-#define CONFIG_RX_DESCR_NUM 8
-#define CONFIG_ETH_BUFSIZE 2048
-#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define CFG_TX_DESCR_NUM 8
+#define CFG_RX_DESCR_NUM 8
+#define CFG_ETH_BUFSIZE 2048
+#define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
/* DMA descriptor. */
struct ag7xxx_dma_desc {
@@ -162,8 +162,8 @@ struct ag7xxx_dma_desc {
};
struct ar7xxx_eth_priv {
- struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
- struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+ struct ag7xxx_dma_desc tx_mac_descrtable[CFG_TX_DESCR_NUM];
+ struct ag7xxx_dma_desc rx_mac_descrtable[CFG_RX_DESCR_NUM];
char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
@@ -408,11 +408,11 @@ static void ag7xxx_dma_clean_tx(struct udevice *dev)
u32 start, end;
int i;
- for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+ for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
curr = &priv->tx_mac_descrtable[i];
- next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
+ next = &priv->tx_mac_descrtable[(i + 1) % CFG_TX_DESCR_NUM];
- curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
+ curr->data_addr = virt_to_phys(&priv->txbuffs[i * CFG_ETH_BUFSIZE]);
curr->config = AG7XXX_DMADESC_IS_EMPTY;
curr->next_desc = virt_to_phys(next);
}
@@ -432,11 +432,11 @@ static void ag7xxx_dma_clean_rx(struct udevice *dev)
u32 start, end;
int i;
- for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+ for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
curr = &priv->rx_mac_descrtable[i];
- next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
+ next = &priv->rx_mac_descrtable[(i + 1) % CFG_RX_DESCR_NUM];
- curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
+ curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CFG_ETH_BUFSIZE]);
curr->config = AG7XXX_DMADESC_IS_EMPTY;
curr->next_desc = virt_to_phys(next);
}
@@ -492,7 +492,7 @@ static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
/* Switch to next TX descriptor. */
- priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
+ priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CFG_TX_DESCR_NUM;
return 0;
}
@@ -543,7 +543,7 @@ static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
flush_dcache_range(start, end);
/* Switch to next RX descriptor. */
- priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
+ priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CFG_RX_DESCR_NUM;
return 0;
}
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ddaf7ed1d38a..e09ca3313dd3 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -38,7 +38,7 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
struct eth_mac_regs *mac_p = priv->mac_regs_p;
ulong start;
u16 miiaddr;
- int timeout = CONFIG_MDIO_TIMEOUT;
+ int timeout = CFG_MDIO_TIMEOUT;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
((reg << MIIREGSHIFT) & MII_REGMSK);
@@ -62,7 +62,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
struct eth_mac_regs *mac_p = priv->mac_regs_p;
ulong start;
u16 miiaddr;
- int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
+ int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
@@ -229,9 +229,9 @@ static void tx_descs_init(struct dw_eth_dev *priv)
struct dmamacdescr *desc_p;
u32 idx;
- for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE];
desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
#if defined(CONFIG_DW_ALTDESCRIPTOR)
@@ -277,9 +277,9 @@ static void rx_descs_init(struct dw_eth_dev *priv)
* GMAC data will be corrupted. */
flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
- for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+ desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE];
desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
desc_p->dmamac_cntl =
@@ -377,7 +377,7 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
start = get_timer(0);
while (readl(&dma_p->busmode) & DMAMAC_SRST) {
- if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
+ if (get_timer(start) >= CFG_MACRESET_TIMEOUT) {
printf("DMA reset timeout\n");
return -ETIMEDOUT;
}
@@ -495,7 +495,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
- if (++desc_num >= CONFIG_TX_DESCR_NUM)
+ if (++desc_num >= CFG_TX_DESCR_NUM)
desc_num = 0;
priv->tx_currdescnum = desc_num;
@@ -555,7 +555,7 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
flush_dcache_range(desc_start, desc_end);
/* Test the wrap-around condition. */
- if (++desc_num >= CONFIG_RX_DESCR_NUM)
+ if (++desc_num >= CFG_RX_DESCR_NUM)
desc_num = 0;
priv->rx_currdescnum = desc_num;
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index 138c3c14bf52..9da4e902cb0d 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -14,14 +14,14 @@
#include <asm-generic/gpio.h>
#endif
-#define CONFIG_TX_DESCR_NUM 16
-#define CONFIG_RX_DESCR_NUM 16
-#define CONFIG_ETH_BUFSIZE 2048
-#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define CFG_TX_DESCR_NUM 16
+#define CFG_RX_DESCR_NUM 16
+#define CFG_ETH_BUFSIZE 2048
+#define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
-#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CFG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
@@ -221,8 +221,8 @@ struct dmamacdescr {
#endif
struct dw_eth_dev {
- struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
- struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+ struct dmamacdescr tx_mac_descrtable[CFG_TX_DESCR_NUM];
+ struct dmamacdescr rx_mac_descrtable[CFG_RX_DESCR_NUM];
char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 0a1fe5609106..38d96ab72b6e 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -168,12 +168,12 @@ struct descriptor { /* A generic descriptor. */
unsigned char params[0];
};
-#define CONFIG_SYS_CMD_SUSPEND 0x4000
-#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
-#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
+#define CFG_SYS_CMD_SUSPEND 0x4000
+#define CFG_SYS_CMD_IAS 0x0001 /* individual address setup */
+#define CFG_SYS_CMD_CONFIGURE 0x0002 /* configure */
-#define CONFIG_SYS_STATUS_C 0x8000
-#define CONFIG_SYS_STATUS_OK 0x2000
+#define CFG_SYS_STATUS_C 0x8000
+#define CFG_SYS_STATUS_OK 0x2000
/* Misc. */
#define NUM_RX_DESC PKTBUFSRX
@@ -411,7 +411,7 @@ static int eepro100_txcmd_send(struct eepro100_priv *priv,
invalidate_dcache_range((unsigned long)desc,
(unsigned long)desc + sizeof(*desc));
rstat = le16_to_cpu(desc->status);
- if (rstat & CONFIG_SYS_STATUS_C)
+ if (rstat & CFG_SYS_STATUS_C)
break;
if (i++ >= TOUT_LOOP) {
@@ -424,7 +424,7 @@ static int eepro100_txcmd_send(struct eepro100_priv *priv,
(unsigned long)desc + sizeof(*desc));
rstat = le16_to_cpu(desc->status);
- if (!(rstat & CONFIG_SYS_STATUS_OK)) {
+ if (!(rstat & CFG_SYS_STATUS_OK)) {
printf("TX error status = 0x%08X\n", rstat);
return -EIO;
}
@@ -577,8 +577,8 @@ static int eepro100_init_common(struct eepro100_priv *priv)
priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
cfg_cmd = &tx_ring[tx_cur];
- cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
- CONFIG_SYS_CMD_CONFIGURE);
+ cfg_cmd->command = cpu_to_le16(CFG_SYS_CMD_SUSPEND |
+ CFG_SYS_CMD_CONFIGURE);
cfg_cmd->status = 0;
cfg_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
(u32)&tx_ring[priv->tx_next]));
@@ -589,7 +589,7 @@ static int eepro100_init_common(struct eepro100_priv *priv)
ret = eepro100_txcmd_send(priv, cfg_cmd);
if (ret) {
if (ret == -ETIMEDOUT)
- printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+ printf("Error---CFG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
goto done;
}
@@ -598,8 +598,8 @@ static int eepro100_init_common(struct eepro100_priv *priv)
priv->tx_next = ((priv->tx_next + 1) % NUM_TX_DESC);
ias_cmd = &tx_ring[tx_cur];
- ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
- CONFIG_SYS_CMD_IAS);
+ ias_cmd->command = cpu_to_le16(CFG_SYS_CMD_SUSPEND |
+ CFG_SYS_CMD_IAS);
ias_cmd->status = 0;
ias_cmd->link = cpu_to_le32(phys_to_bus(priv->devno,
(u32)&tx_ring[priv->tx_next]));
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ab52cc119f4e..006d27051ebe 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
* sending and after receiving.
*/
#ifdef CONFIG_MX28
-#define CONFIG_FEC_MXC_SWAP_PACKET
+#define CFG_FEC_MXC_SWAP_PACKET
#endif
#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
@@ -76,7 +76,7 @@ DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
static void swap_packet(uint32_t *packet, int length)
{
int i;
@@ -685,7 +685,7 @@ static int fecmxc_send(struct udevice *dev, void *packet, int length)
* transmission, the second will be empty and only used to stop the DMA
* engine. We also flush the packet to RAM here to avoid cache trouble.
*/
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)packet, length);
#endif
@@ -875,7 +875,7 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
invalidate_dcache_range(addr, end);
/* Fill the buffer and pass it to upper layers */
-#ifdef CONFIG_FEC_MXC_SWAP_PACKET
+#ifdef CFG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)addr, frame_length);
#endif
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 055dd61fbe5a..fcb5cc89f18b 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -361,7 +361,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
if (src == BOOT_SOURCE_IFC_NOR) {
addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
- CONFIG_SYS_FSL_IFC_BASE);
+ CFG_SYS_FSL_IFC_BASE);
#ifdef CONFIG_CMD_NAND
} else if (src == BOOT_SOURCE_IFC_NAND) {
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 48dd558405c5..eae20654513e 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -32,11 +32,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
(REG & 0x1f) << 18) | (VAL & 0xffff))
-#ifndef CONFIG_SYS_UNSPEC_PHYID
-# define CONFIG_SYS_UNSPEC_PHYID 0
+#ifndef CFG_SYS_UNSPEC_PHYID
+# define CFG_SYS_UNSPEC_PHYID 0
#endif
-#ifndef CONFIG_SYS_UNSPEC_STRID
-# define CONFIG_SYS_UNSPEC_STRID 0
+#ifndef CFG_SYS_UNSPEC_STRID
+# define CFG_SYS_UNSPEC_STRID 0
#endif
typedef struct phy_info_struct {
@@ -58,8 +58,8 @@ phy_info_t phyinfo[] = {
{0x20005C90, "N83848"}, /* National 83848 */
{0x20005CA2, "N83849"}, /* National 83849 */
{0x01814400, "QS6612"}, /* QS6612 */
-#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
- {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
+#if defined(CFG_SYS_UNSPEC_PHYID) && defined(CFG_SYS_UNSPEC_STRID)
+ {CFG_SYS_UNSPEC_PHYID, CFG_SYS_UNSPEC_STRID},
#endif
{0, 0}
};
diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c
index 50d066a8ba2f..0a9bdb3ddbd6 100644
--- a/drivers/net/mt7628-eth.c
+++ b/drivers/net/mt7628-eth.c
@@ -127,9 +127,9 @@ struct fe_tx_dma {
#define MTK_QDMA_PAGE_SIZE 2048
-#define CONFIG_MDIO_TIMEOUT 100
-#define CONFIG_DMA_STOP_TIMEOUT 100
-#define CONFIG_TX_DMA_TIMEOUT 100
+#define CFG_MDIO_TIMEOUT 100
+#define CFG_DMA_STOP_TIMEOUT 100
+#define CFG_TX_DMA_TIMEOUT 100
struct mt7628_eth_dev {
void __iomem *base; /* frame engine base address */
@@ -162,7 +162,7 @@ static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set)
int ret;
ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set,
- CONFIG_MDIO_TIMEOUT, false);
+ CFG_MDIO_TIMEOUT, false);
if (ret) {
printf("MDIO operation timeout!\n");
return -ETIMEDOUT;
@@ -352,7 +352,7 @@ static void eth_dma_stop(struct mt7628_eth_dev *priv)
/* Wait for DMA to stop */
ret = wait_for_bit_le32(base + PDMA_GLO_CFG,
RX_DMA_BUSY | TX_DMA_BUSY, false,
- CONFIG_DMA_STOP_TIMEOUT, false);
+ CFG_DMA_STOP_TIMEOUT, false);
if (ret)
printf("DMA stop timeout error!\n");
}
@@ -399,7 +399,7 @@ static int mt7628_eth_send(struct udevice *dev, void *packet, int length)
/* Check if buffer is ready for next TX DMA */
ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true,
- CONFIG_TX_DMA_TIMEOUT, false);
+ CFG_TX_DMA_TIMEOUT, false);
if (ret) {
printf("TX: DMA still busy on buffer %d\n", idx);
return ret;
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 7e1922e1c485..1bad50d344c7 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -587,7 +587,7 @@ enum mv_netc_lanes {
/* Default number of RXQs in use */
#define MVPP2_DEFAULT_RXQ 1
-#define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
+#define CFG_MV_ETH_RXQ 8 /* increment by 8 */
/* Max number of Rx descriptors */
#define MVPP2_MAX_RXD 16
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 1e52917ff2c3..151bc55e076b 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -11,11 +11,11 @@
#include <stdio_dev.h>
#include <net.h>
-#ifndef CONFIG_NETCONSOLE_BUFFER_SIZE
-#define CONFIG_NETCONSOLE_BUFFER_SIZE 512
+#ifndef CFG_NETCONSOLE_BUFFER_SIZE
+#define CFG_NETCONSOLE_BUFFER_SIZE 512
#endif
-static char input_buffer[CONFIG_NETCONSOLE_BUFFER_SIZE];
+static char input_buffer[CFG_NETCONSOLE_BUFFER_SIZE];
static int input_size; /* char count in input buffer */
static int input_offset; /* offset to valid chars in input buffer */
static int input_recursion;
diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c
index bd29a10def84..2028f4ae286e 100644
--- a/drivers/net/npcm750_eth.c
+++ b/drivers/net/npcm750_eth.c
@@ -18,15 +18,15 @@
#include <linux/iopoll.h>
#define MAC_ADDR_SIZE 6
-#define CONFIG_TX_DESCR_NUM 32
-#define CONFIG_RX_DESCR_NUM 32
+#define CFG_TX_DESCR_NUM 32
+#define CFG_RX_DESCR_NUM 32
#define TX_TOTAL_BUFSIZE \
- ((CONFIG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
+ ((CFG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
#define RX_TOTAL_BUFSIZE \
- ((CONFIG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
+ ((CFG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
-#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
struct npcm750_rxbd {
unsigned int sl;
@@ -101,8 +101,8 @@ struct emc_regs {
};
struct npcm750_eth_dev {
- struct npcm750_txbd tdesc[CONFIG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
- struct npcm750_rxbd rdesc[CONFIG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
+ struct npcm750_txbd tdesc[CFG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
+ struct npcm750_rxbd rdesc[CFG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
struct emc_regs *emc_regs_p;
@@ -279,7 +279,7 @@ static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs)
struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
struct emc_regs *reg = priv->emc_regs_p;
u32 start, val;
- int timeout = CONFIG_MDIO_TIMEOUT;
+ int timeout = CFG_MDIO_TIMEOUT;
val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20);
writel(val, ®->miida);
@@ -301,7 +301,7 @@ static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs
struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
struct emc_regs *reg = priv->emc_regs_p;
ulong start;
- int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
+ int ret = -ETIMEDOUT, timeout = CFG_MDIO_TIMEOUT;
writel(val, ®->miid);
writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), ®->miida);
@@ -354,19 +354,19 @@ static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv)
writel((u32)desc_table_p, ®->txdlsa);
priv->curr_txd = desc_table_p;
- for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN];
desc_p->sl = 0;
desc_p->mode = 0;
desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN;
- if (idx < (CONFIG_TX_DESCR_NUM - 1))
+ if (idx < (CFG_TX_DESCR_NUM - 1))
desc_p->next = (u32)&desc_table_p[idx + 1];
else
desc_p->next = (u32)&priv->tdesc[0];
}
flush_dcache_range((ulong)&desc_table_p[0],
- (ulong)&desc_table_p[CONFIG_TX_DESCR_NUM]);
+ (ulong)&desc_table_p[CFG_TX_DESCR_NUM]);
}
static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
@@ -378,22 +378,22 @@ static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
u32 idx;
flush_dcache_range((ulong)priv->rxbuffs[0],
- (ulong)priv->rxbuffs[CONFIG_RX_DESCR_NUM]);
+ (ulong)priv->rxbuffs[CFG_RX_DESCR_NUM]);
writel((u32)desc_table_p, ®->rxdlsa);
priv->curr_rxd = desc_table_p;
- for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+ for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->sl = RX_OWEN_DMA;
desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN];
- if (idx < (CONFIG_RX_DESCR_NUM - 1))
+ if (idx < (CFG_RX_DESCR_NUM - 1))
desc_p->next = (u32)&desc_table_p[idx + 1];
else
desc_p->next = (u32)&priv->rdesc[0];
}
flush_dcache_range((ulong)&desc_table_p[0],
- (ulong)&desc_table_p[CONFIG_RX_DESCR_NUM]);
+ (ulong)&desc_table_p[CFG_RX_DESCR_NUM]);
}
static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv)
diff --git a/drivers/net/octeon/octeon_eth.c b/drivers/net/octeon/octeon_eth.c
index fbb1afc08abc..659ba51ecb4a 100644
--- a/drivers/net/octeon/octeon_eth.c
+++ b/drivers/net/octeon/octeon_eth.c
@@ -58,7 +58,7 @@
#include <mach/cvmx-mdio.h>
/** Maximum receive packet size (hardware default is 1536) */
-#define CONFIG_OCTEON_NETWORK_MRU 1536
+#define CFG_OCTEON_NETWORK_MRU 1536
#define OCTEON_BOOTLOADER_NAMED_BLOCK_TMP_PREFIX "__tmp"
@@ -199,7 +199,7 @@ static void cvm_oct_fill_hw_memory(u64 pool, u64 size, u64 elements)
*/
static void cvm_oct_configure_common_hw(void)
{
- int mru = env_get_ulong("octeon_mru", 0, CONFIG_OCTEON_NETWORK_MRU);
+ int mru = env_get_ulong("octeon_mru", 0, CFG_OCTEON_NETWORK_MRU);
int packet_pool_size = CVMX_FPA_PACKET_POOL_SIZE;
if (mru > packet_pool_size)
@@ -224,7 +224,7 @@ static void cvm_oct_configure_common_hw(void)
cvmx_helper_initialize_packet_io_local();
/* The MRU defaults to 1536 bytes by the hardware. Setting
- * CONFIG_OCTEON_NETWORK_MRU allows this to be overridden.
+ * CFG_OCTEON_NETWORK_MRU allows this to be overridden.
*/
if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
struct cvmx_pki_global_config gbl_cfg;
diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c
index 8fec1c21e10f..6d1509d90cf0 100644
--- a/drivers/net/qe/dm_qe_uec.c
+++ b/drivers/net/qe/dm_qe_uec.c
@@ -20,8 +20,8 @@
#define QE_UEC_DRIVER_NAME "ucc_geth"
/* Default UTBIPAR SMI address */
-#ifndef CONFIG_UTBIPAR_INIT_TBIPA
-#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
+#ifndef CFG_UTBIPAR_INIT_TBIPA
+#define CFG_UTBIPAR_INIT_TBIPA 0x1F
#endif
static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
@@ -840,10 +840,10 @@ static int uec_startup(struct udevice *dev)
utbipar = in_be32(&uec_regs->utbipar);
utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
- /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
+ /* Initialize UTBIPAR address to CFG_UTBIPAR_INIT_TBIPA for ALL UEC.
* This frees up the remaining SMI addresses for use.
*/
- utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
+ utbipar |= CFG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
out_be32(&uec_regs->utbipar, utbipar);
/* Allocate Tx BDs */
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 9cca8fa4e0a1..e800a326b81e 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -43,19 +43,19 @@
#define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
#define MDIO_CMD_MII_CLK_CSR_SHIFT 20
-#define CONFIG_TX_DESCR_NUM 32
-#define CONFIG_RX_DESCR_NUM 32
-#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
+#define CFG_TX_DESCR_NUM 32
+#define CFG_RX_DESCR_NUM 32
+#define CFG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
/*
* The datasheet says that each descriptor can transfers up to 4096 bytes
* But later, the register documentation reduces that value to 2048,
* using 2048 cause strange behaviours and even BSP driver use 2047
*/
-#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
+#define CFG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
-#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
-#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+#define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
#define H3_EPHY_DEFAULT_VALUE 0x58000
#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
@@ -75,7 +75,7 @@
#define SC_ERXDC_MASK GENMASK(9, 5)
#define SC_ERXDC_OFFSET 5
-#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
+#define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
#define AHB_GATE_OFFSET_EPHY 0
@@ -143,8 +143,8 @@ struct emac_dma_desc {
} __aligned(ARCH_DMA_MINALIGN);
struct emac_eth_dev {
- struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
- struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
+ struct emac_dma_desc rx_chain[CFG_TX_DESCR_NUM];
+ struct emac_dma_desc tx_chain[CFG_RX_DESCR_NUM];
char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
@@ -209,7 +209,7 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
MDIO_CMD_MII_BUSY, false,
- CONFIG_MDIO_TIMEOUT, true);
+ CFG_MDIO_TIMEOUT, true);
if (ret < 0)
return ret;
@@ -244,7 +244,7 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
MDIO_CMD_MII_BUSY, false,
- CONFIG_MDIO_TIMEOUT, true);
+ CFG_MDIO_TIMEOUT, true);
}
static int sun8i_eth_write_hwaddr(struct udevice *dev)
@@ -412,11 +412,11 @@ static void rx_descs_init(struct emac_eth_dev *priv)
invalidate_dcache_range((uintptr_t)rxbuffs,
(uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
- for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+ for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
desc_p = &desc_table_p[i];
- desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
+ desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CFG_ETH_BUFSIZE];
desc_p->next = (uintptr_t)&desc_table_p[i + 1];
- desc_p->ctl_size = CONFIG_ETH_RXSIZE;
+ desc_p->ctl_size = CFG_ETH_RXSIZE;
desc_p->status = EMAC_DESC_OWN_DMA;
}
@@ -438,9 +438,9 @@ static void tx_descs_init(struct emac_eth_dev *priv)
struct emac_dma_desc *desc_p;
int i;
- for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+ for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
desc_p = &desc_table_p[i];
- desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
+ desc_p->buf_addr = (uintptr_t)&txbuffs[i * CFG_ETH_BUFSIZE];
desc_p->next = (uintptr_t)&desc_table_p[i + 1];
desc_p->ctl_size = 0;
desc_p->status = 0;
@@ -541,7 +541,7 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
return 0;
}
- if (length > CONFIG_ETH_RXSIZE) {
+ if (length > CFG_ETH_RXSIZE) {
debug("RX: Too large packet (%d bytes)\n", length);
return 0;
}
@@ -575,7 +575,7 @@ static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
cache_clean_descriptor(desc_p);
/* Move to next Descriptor and wrap around */
- if (++desc_num >= CONFIG_TX_DESCR_NUM)
+ if (++desc_num >= CFG_TX_DESCR_NUM)
desc_num = 0;
priv->tx_currdescnum = desc_num;
@@ -701,7 +701,7 @@ static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
cache_clean_descriptor(desc_p);
/* Move to next desc and wrap-around condition. */
- if (++desc_num >= CONFIG_RX_DESCR_NUM)
+ if (++desc_num >= CFG_RX_DESCR_NUM)
desc_num = 0;
priv->rx_currdescnum = desc_num;
diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c
index 2dfadbd82d5b..29d2fc9b54e9 100644
--- a/drivers/net/ti/davinci_emac.c
+++ b/drivers/net/ti/davinci_emac.c
@@ -65,8 +65,8 @@ static inline unsigned long HW_TO_BD(unsigned long x)
#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
#endif
-#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
-#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
+#if !defined(CFG_SYS_EMAC_TI_CLKDIV)
+#define CFG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
EMAC_MDIO_CLOCK_FREQ) - 1)
#endif
@@ -98,17 +98,17 @@ static int emac_rx_queue_active = 0;
static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
__aligned(ARCH_DMA_MINALIGN);
-#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
-#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
+#ifndef CFG_SYS_DAVINCI_EMAC_PHY_COUNT
+#define CFG_SYS_DAVINCI_EMAC_PHY_COUNT 3
#endif
/* PHY address for a discovered PHY (0xff - not found) */
-static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+static u_int8_t active_phy_addr[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
/* number of PHY found active */
static u_int8_t num_phy;
-phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
+phy_t phy[CFG_SYS_DAVINCI_EMAC_PHY_COUNT];
static int davinci_emac_write_hwaddr(struct udevice *dev)
{
@@ -152,7 +152,7 @@ static void davinci_eth_mdio_enable(void)
{
u_int32_t clkdiv;
- clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+ clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) |
MDIO_CONTROL_ENABLE |
@@ -176,7 +176,7 @@ static int davinci_eth_phy_detect(void)
int j;
unsigned int count = 0;
- for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
+ for (i = 0; i < CFG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
active_phy_addr[i] = 0xff;
udelay(1000);
@@ -190,7 +190,7 @@ static int davinci_eth_phy_detect(void)
for (i = 0, j = 0; i < 32; i++)
if (phy_act_state & (1 << i)) {
count++;
- if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
+ if (count <= CFG_SYS_DAVINCI_EMAC_PHY_COUNT) {
active_phy_addr[j++] = i;
} else {
printf("%s: to many PHYs detected.\n",
@@ -501,7 +501,7 @@ static int davinci_emac_start(struct udevice *dev)
writel(1, &adap_emac->RXUNICASTSET);
/* Init MDIO & get link state */
- clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
+ clkdiv = CFG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
&adap_mdio->CONTROL);
diff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c
index 82010e7c96e7..27a312227bc0 100644
--- a/drivers/phy/phy-ti-am654.c
+++ b/drivers/phy/phy-ti-am654.c
@@ -28,8 +28,8 @@
#define CMU_MASTER_CDN_O BIT(24)
#define COMLANE_R138 0xb38
-#define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
-#define CONFIG_VERSION_REG_SHIFT 16
+#define CFG_VERSION_REG_MASK GENMASK(23, 16)
+#define CFG_VERSION_REG_SHIFT 16
#define VERSION 0x70
#define COMLANE_R190 0xb90
@@ -286,8 +286,8 @@ static int serdes_am654_init(struct phy *x)
u32 mask;
u32 val;
- mask = CONFIG_VERSION_REG_MASK;
- val = VERSION << CONFIG_VERSION_REG_SHIFT;
+ mask = CFG_VERSION_REG_MASK;
+ val = VERSION << CFG_VERSION_REG_SHIFT;
regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
val = CMU_MASTER_CDN_O;
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
index 947975ee72a7..fa4c084e2fc0 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.h
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -45,7 +45,7 @@ extern const struct pinctrl_ops imx_pinctrl_ops;
#define SHARE_MUX_CONF_REG 0x1
#define ZERO_OFFSET_VALID 0x2
-#define CONFIG_IBE_OBE 0x4
+#define CFG_IBE_OBE 0x4
#define IMX8_USE_SCU 0x8
#define IOMUXC_CONFIG_SION (0x1 << 4)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
index da0f6c9ba0e5..6da9ff7c5bce 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
@@ -12,11 +12,11 @@
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info0 = {
- .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
};
static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info1 = {
- .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
};
static int imx7ulp_pinctrl_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
index 3f15f1dd4502..4e8fa08bc6e3 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
@@ -11,11 +11,11 @@
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info0 = {
- .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
};
static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info1 = {
- .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CONFIG_IBE_OBE,
+ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
};
static int imx8ulp_pinctrl_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c
index 9a54b8bbe902..eb90e28d4b21 100644
--- a/drivers/pinctrl/nxp/pinctrl-mxs.c
+++ b/drivers/pinctrl/nxp/pinctrl-mxs.c
@@ -94,9 +94,9 @@ static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
config = mxs_dt_node_to_map(conf);
- ma = CONFIG_TO_MA(config);
- vol = CONFIG_TO_VOL(config);
- pull = CONFIG_TO_PULL(config);
+ ma = CFG_TO_MA(config);
+ vol = CFG_TO_VOL(config);
+ pull = CFG_TO_PULL(config);
for (i = 0; i < npins; i++) {
int pinid, bank, pin, shift;
diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.h b/drivers/pinctrl/nxp/pinctrl-mxs.h
index a398e43cbebb..20d6dea33893 100644
--- a/drivers/pinctrl/nxp/pinctrl-mxs.h
+++ b/drivers/pinctrl/nxp/pinctrl-mxs.h
@@ -43,9 +43,9 @@
#define VOL_SHIFT 3
#define MA_PRESENT (1 << 2)
#define MA_SHIFT 0
-#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
-#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
-#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
+#define CFG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
+#define CFG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
+#define CFG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
struct mxs_regs {
u16 muxsel;
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 7c5a02db1b98..ee6529b3c295 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -73,7 +73,7 @@ struct zynqmp_pinctrl_config {
/**
* enum zynqmp_pin_config_param - possible pin configuration parameters
- * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard,
+ * @PIN_CFG_IOSTANDARD: if the pin can select an IO standard,
* the argument to this parameter (on a
* custom format) tells the driver which
* alternative IO standard to use
@@ -81,7 +81,7 @@ struct zynqmp_pinctrl_config {
* to select schmitt or cmos input for MIO pins
*/
enum zynqmp_pin_config_param {
- PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1,
+ PIN_CFG_IOSTANDARD = PIN_CONFIG_END + 1,
PIN_CONFIG_SCHMITTCMOS,
};
@@ -452,7 +452,7 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
ret = zynqmp_pm_pinctrl_set_config(pin, param, value);
break;
- case PIN_CONFIG_IOSTANDARD:
+ case PIN_CFG_IOSTANDARD:
param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
if (arg != value)
@@ -608,7 +608,7 @@ static const struct pinconf_param zynqmp_conf_params[] = {
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
{ "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
/* zynqmp specific */
- {"io-standard", PIN_CONFIG_IOSTANDARD, IO_STANDARD_LVCMOS18},
+ {"io-standard", PIN_CFG_IOSTANDARD, IO_STANDARD_LVCMOS18},
{"schmitt-cmos", PIN_CONFIG_SCHMITTCMOS, PM_PINCTRL_INPUT_TYPE_SCHMITT},
};
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index fb1f683f9bd4..2825dc6f9aa6 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -185,7 +185,7 @@ void qe_init(uint qe_base)
* which do not have ROM in QE.
*/
qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
- CONFIG_SYS_FSL_IFC_BASE));
+ CFG_SYS_FSL_IFC_BASE));
/* enable the microcode in IRAM */
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
@@ -234,7 +234,7 @@ void u_qe_init(void)
if (src == BOOT_SOURCE_IFC_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
- CONFIG_SYS_FSL_IFC_BASE);
+ CFG_SYS_FSL_IFC_BASE);
if (src == BOOT_SOURCE_QSPI_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index a2d7ca82fc01..18767554123f 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -104,10 +104,10 @@
* -> WL = AL + CWL + PL = CWL
* -> RL = AL + CL + PL = CL
*/
-#define CONFIG_WL 9
-#define CONFIG_RL 12
-#define T_RDDATA_EN ((CONFIG_RL - 2) << 8)
-#define T_PHY_WRLAT (CONFIG_WL - 2)
+#define CFG_WL 9
+#define CFG_RL 12
+#define T_RDDATA_EN ((CFG_RL - 2) << 8)
+#define T_PHY_WRLAT (CFG_WL - 2)
/* MR0 */
#define MR0_CL_12 (BIT(4) | BIT(2))
@@ -974,8 +974,8 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
/* update CL and WL */
reg = readl(®s->ac_timing[1]);
reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING);
- reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) |
- FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5);
+ reg |= FIELD_PREP(SDRAM_WL_SETTING, CFG_WL - 5) |
+ FIELD_PREP(SDRAM_CL_SETTING, CFG_RL - 5);
writel(reg, ®s->ac_timing[1]);
writel(DDR4_MR01_MODE, ®s->mr01_mode_setting);
diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c
index bb21078df140..ff2899d74843 100644
--- a/drivers/ram/octeon/octeon_ddr.c
+++ b/drivers/ram/octeon/octeon_ddr.c
@@ -17,7 +17,7 @@
#include <mach/octeon_ddr.h>
-#define CONFIG_REF_HERTZ 50000000
+#define CFG_REF_HERTZ 50000000
DECLARE_GLOBAL_DATA_PTR;
@@ -152,7 +152,7 @@ static void cvmx_l2c_set_big_size(struct ddr_priv *priv, u64 mem_size, int mode)
static u32 octeon3_refclock(u32 alt_refclk, u32 ddr_hertz,
struct dimm_config *dimm_config)
{
- u32 ddr_ref_hertz = CONFIG_REF_HERTZ;
+ u32 ddr_ref_hertz = CFG_REF_HERTZ;
int ddr_type;
int spd_dimm_type;
@@ -2453,7 +2453,7 @@ try_again:
} else {
if (ddr_ref_hertz == 100000000) {
debug("N0: DRAM init: requested 100 MHz refclk NOT SUPPORTED\n");
- ddr_ref_hertz = CONFIG_REF_HERTZ;
+ ddr_ref_hertz = CFG_REF_HERTZ;
}
}
@@ -2486,7 +2486,7 @@ try_again:
if (hertz_diff > ((int)ddr_hertz * 5 / 100)) {
// nope, diff is greater than than 5%
debug("N0: DRAM init: requested 100 MHz refclk NOT FOUND\n");
- ddr_ref_hertz = CONFIG_REF_HERTZ;
+ ddr_ref_hertz = CFG_REF_HERTZ;
// clear the flag before trying again!!
set_ddr_clock_initialized(priv, 0, 0);
goto try_again;
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 6929a7e494ee..dd5b19174455 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -109,7 +109,7 @@ enum {
PCTL_STAT_MSK = 7,
INIT_MEM = 0,
CONFIG,
- CONFIG_REQ,
+ CFG_REQ,
ACCESS,
ACCESS_REQ,
LOW_POWER,
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 772dd6fef8f3..eab9537fbae5 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,9 +52,9 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#endif
-#ifndef CONFIG_SYS_NS16550_IER
-#define CONFIG_SYS_NS16550_IER 0x00
-#endif /* CONFIG_SYS_NS16550_IER */
+#ifndef CFG_SYS_NS16550_IER
+#define CFG_SYS_NS16550_IER 0x00
+#endif /* CFG_SYS_NS16550_IER */
static inline void serial_out_shift(void *addr, int shift, int value)
{
@@ -251,7 +251,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor)
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
- serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
+ serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
@@ -275,7 +275,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor)
#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
{
- serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
+ serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
ns16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
@@ -340,7 +340,7 @@ static inline void _debug_uart_init(void)
*/
baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE);
- serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+ serial_dout(&com_port->ier, CFG_SYS_NS16550_IER);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 904f7d21bf03..26310b0b7464 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -21,8 +21,8 @@
#ifdef CONFIG_DEBUG_UART_OMAP
-#ifndef CONFIG_SYS_NS16550_IER
-#define CONFIG_SYS_NS16550_IER 0x00
+#ifndef CFG_SYS_NS16550_IER
+#define CFG_SYS_NS16550_IER 0x00
#endif
#define UART_MCRVAL 0x00
@@ -71,7 +71,7 @@ static inline void _debug_uart_init(void)
baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE);
- serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+ serial_dout(&com_port->ier, CFG_SYS_NS16550_IER);
serial_dout(&com_port->mdr1, 0x7);
serial_dout(&com_port->mcr, UART_MCRVAL);
serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 07a59ec9607a..ecb6ba853df7 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -45,8 +45,8 @@
#define GSERIAL_RX_ENDPOINT 1
#define NUM_ACM_INTERFACES 2
#define NUM_GSERIAL_INTERFACES 1
-#define CONFIG_USBD_DATA_INTERFACE_STR "Bulk Data Interface"
-#define CONFIG_USBD_CTRL_INTERFACE_STR "Control Interface"
+#define CFG_USBD_DATA_INTERFACE_STR "Bulk Data Interface"
+#define CFG_USBD_CTRL_INTERFACE_STR "Control Interface"
/*
* Buffers to hold input and output data
@@ -97,9 +97,9 @@ static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4};
static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)];
static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)];
static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)];
-static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)];
-static u8 wstrDataInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
-static u8 wstrCtrlInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
+static u8 wstrConfiguration[2 + 2*(sizeof(CFG_USBD_CONFIGURATION_STR)-1)];
+static u8 wstrDataInterface[2 + 2*(sizeof(CFG_USBD_DATA_INTERFACE_STR)-1)];
+static u8 wstrCtrlInterface[2 + 2*(sizeof(CFG_USBD_DATA_INTERFACE_STR)-1)];
/* Standard USB Data Structures */
static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES];
@@ -206,7 +206,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
.bEndpointAddress = UDC_INT_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_INT,
.wMaxPacketSize
- = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+ = cpu_to_le16(CFG_USBD_SERIAL_INT_PKTSIZE),
.bInterval = 0xFF,
},
@@ -233,7 +233,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
.bmAttributes =
USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
- cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+ cpu_to_le16(CFG_USBD_SERIAL_BULK_PKTSIZE),
.bInterval = 0xFF,
},
{
@@ -244,7 +244,7 @@ static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
.bmAttributes =
USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
- cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+ cpu_to_le16(CFG_USBD_SERIAL_BULK_PKTSIZE),
.bInterval = 0xFF,
},
},
@@ -312,7 +312,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
.bEndpointAddress = UDC_OUT_ENDPOINT | USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
- cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE),
+ cpu_to_le16(CFG_USBD_SERIAL_OUT_PKTSIZE),
.bInterval= 0xFF,
},
{
@@ -322,7 +322,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
.bEndpointAddress = UDC_IN_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
- cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
+ cpu_to_le16(CFG_USBD_SERIAL_IN_PKTSIZE),
.bInterval = 0xFF,
},
{
@@ -332,7 +332,7 @@ gserial_configuration_descriptors[NUM_CONFIGS] ={
.bEndpointAddress = UDC_INT_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_INT,
.wMaxPacketSize =
- cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+ cpu_to_le16(CFG_USBD_SERIAL_INT_PKTSIZE),
.bInterval = 0xFF,
},
},
@@ -594,20 +594,20 @@ static void usbtty_init_strings (void)
string = (struct usb_string_descriptor *) wstrConfiguration;
string->bLength = sizeof(wstrConfiguration);
string->bDescriptorType = USB_DT_STRING;
- str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData);
+ str2wide (CFG_USBD_CONFIGURATION_STR, string->wData);
usbtty_string_table[STR_CONFIG]=string;
string = (struct usb_string_descriptor *) wstrDataInterface;
string->bLength = sizeof(wstrDataInterface);
string->bDescriptorType = USB_DT_STRING;
- str2wide (CONFIG_USBD_DATA_INTERFACE_STR, string->wData);
+ str2wide (CFG_USBD_DATA_INTERFACE_STR, string->wData);
usbtty_string_table[STR_DATA_INTERFACE]=string;
string = (struct usb_string_descriptor *) wstrCtrlInterface;
string->bLength = sizeof(wstrCtrlInterface);
string->bDescriptorType = USB_DT_STRING;
- str2wide (CONFIG_USBD_CTRL_INTERFACE_STR, string->wData);
+ str2wide (CFG_USBD_CTRL_INTERFACE_STR, string->wData);
usbtty_string_table[STR_CTRL_INTERFACE]=string;
/* Now, initialize the string table for ep0 handling */
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index 8c7e61b2ca27..b176a7961b8f 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -20,17 +20,17 @@
#include <usb/udc.h>
#include <version.h>
-#ifndef CONFIG_USBD_CONFIGURATION_STR
-#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB"
+#ifndef CFG_USBD_CONFIGURATION_STR
+#define CFG_USBD_CONFIGURATION_STR "TTY via USB"
#endif
-#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
-#define CONFIG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE
-#define CONFIG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT
-#define CONFIG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE
-#define CONFIG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
-#define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE
-#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE
+#define CFG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
+#define CFG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE
+#define CFG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT
+#define CFG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE
+#define CFG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
+#define CFG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE
+#define CFG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE
#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index ea9cc3d1f983..840660ffe9a3 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -101,8 +101,8 @@ __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
#define reg_read readl
#define reg_write(a, v) writel(v, a)
-#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
-#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
+#if !defined(CFG_SYS_SPI_MXC_WAIT)
+#define CFG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
#endif
#define MAX_CS_COUNT 4
@@ -371,7 +371,7 @@ int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
status = reg_read(®s->stat);
/* Wait until the TC (Transfer completed) bit is set */
while ((status & MXC_CSPICTRL_TC) == 0) {
- if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
+ if (get_timer(ts) > CFG_SYS_SPI_MXC_WAIT) {
printf("spi_xchg_single: Timeout!\n");
return -1;
}
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c
index 410bf723d6b4..7814cb6a5d61 100644
--- a/drivers/timer/mpc83xx_timer.c
+++ b/drivers/timer/mpc83xx_timer.c
@@ -20,8 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#ifndef CFG_SYS_WATCHDOG_FREQ
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
#endif
/**
@@ -175,7 +175,7 @@ void timer_interrupt(struct pt_regs *regs)
priv->timestamp++;
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
- if (CONFIG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
+ if (CFG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0)
schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 069888fdd906..8a38832b05f8 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -898,7 +898,7 @@ enum {
#define RESET_LEVEL 0xFF
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
-#define CONFIG_RESULT_CODE_MASK 0xFF
+#define CFG_RESULT_CODE_MASK 0xFF
#define GENERIC_ERROR_CODE_MASK 0xFF
#define ufshcd_writel(hba, val, reg) \
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index d9a89a17b27e..b9258d735757 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -322,7 +322,7 @@ static void ep_enable(int num, int in, int maxpacket)
if (num != 0) {
struct ept_queue_head *head = ci_get_qh(num, in);
- head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
+ head->config = CFG_MAX_PKT(maxpacket) | CFG_ZLT;
ci_flush_qh(num);
}
writel(n, &udc->epctrl[num]);
@@ -959,11 +959,11 @@ static int ci_udc_probe(void)
*/
head = controller.epts + i;
if (i < 2)
- head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
- | CONFIG_ZLT | CONFIG_IOS;
+ head->config = CFG_MAX_PKT(EP0_MAX_PACKET_SIZE)
+ | CFG_ZLT | CFG_IOS;
else
- head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
- | CONFIG_ZLT;
+ head->config = CFG_MAX_PKT(EP_MAX_PACKET_SIZE)
+ | CFG_ZLT;
head->next = TERMINATE;
head->info = 0;
diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h
index 95cc07992b41..bea2f9f3fe33 100644
--- a/drivers/usb/gadget/ci_udc.h
+++ b/drivers/usb/gadget/ci_udc.h
@@ -128,9 +128,9 @@ struct ept_queue_head {
unsigned reserved_4;
};
-#define CONFIG_MAX_PKT(n) ((n) << 16)
-#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
-#define CONFIG_IOS (1 << 15) /* IRQ on setup */
+#define CFG_MAX_PKT(n) ((n) << 16)
+#define CFG_ZLT (1 << 29) /* stop on zero-len xfer */
+#define CFG_IOS (1 << 15) /* IRQ on setup */
struct ept_queue_item {
unsigned next;
diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c
index b61b5382df41..85a352696019 100644
--- a/drivers/usb/host/ehci-faraday.c
+++ b/drivers/usb/host/ehci-faraday.c
@@ -16,8 +16,8 @@
#include "ehci.h"
-#ifndef CONFIG_USB_EHCI_BASE_LIST
-#define CONFIG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
+#ifndef CFG_USB_EHCI_BASE_LIST
+#define CFG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
#endif
union ehci_faraday_regs {
@@ -93,7 +93,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
union ehci_faraday_regs *regs;
- uint32_t base_list[] = CONFIG_USB_EHCI_BASE_LIST;
+ uint32_t base_list[] = CFG_USB_EHCI_BASE_LIST;
if (index < 0 || index >= ARRAY_SIZE(base_list))
return -1;
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index b02ee89c3eca..11d776747c04 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -578,8 +578,8 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
#ifdef CONFIG_USB_ULPI
/* if board file does not set a ULPI reference frequency we default to 24MHz */
-#ifndef CONFIG_ULPI_REF_CLK
-#define CONFIG_ULPI_REF_CLK 24000000
+#ifndef CFG_ULPI_REF_CLK
+#define CFG_ULPI_REF_CLK 24000000
#endif
/* set up the ULPI USB controller with the parameters provided */
@@ -594,7 +594,7 @@ static int init_ulpi_usb_controller(struct fdt_usb *config,
/* set up ULPI reference clock on pllp_out4 */
clock_enable(PERIPH_ID_DEV2_OUT);
- clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
+ clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CFG_ULPI_REF_CLK);
/* reset ULPI phy */
if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h
index 6d9f19dfe6b3..8829567bfb68 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -16,11 +16,11 @@
* Map U-Boot config options to Linux ones
*/
#ifdef CONFIG_OMAP34XX
-#define CONFIG_SOC_OMAP3430
+#define CFG_SOC_OMAP3430
#endif
#ifdef CONFIG_OMAP44XX
-#define CONFIG_ARCH_OMAP4
+#define CFG_ARCH_OMAP4
#endif
#endif /* __LINUX_COMPAT_H__ */
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index fc7af7484e4c..a42d98ece9b1 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1525,8 +1525,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
/*-------------------------------------------------------------------------*/
-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
- defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
+#if defined(CONFIG_SOC_OMAP2430) || defined(CFG_SOC_OMAP3430) || \
+ defined(CFG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
static irqreturn_t generic_interrupt(int irq, void *__hci)
{
diff --git a/drivers/usb/musb-new/musb_core.h b/drivers/usb/musb-new/musb_core.h
index 821d0e06f619..adfd81b85448 100644
--- a/drivers/usb/musb-new/musb_core.h
+++ b/drivers/usb/musb-new/musb_core.h
@@ -151,7 +151,7 @@ enum musb_g_ep0_state {
*/
#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
- || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_ARCH_OMAP4)
+ || defined(CFG_SOC_OMAP3430) || defined(CFG_ARCH_OMAP4)
/* REVISIT indexed access seemed to
* misbehave (on DaVinci) for at least peripheral IN ...
*/
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 8b930e3fa919..8d71db04a2d7 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -22,7 +22,7 @@
*/
static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
{
- int timeout = CONFIG_USB_ULPI_TIMEOUT;
+ int timeout = CFG_USB_ULPI_TIMEOUT;
while (--timeout) {
if (!(readl(ulpi_vp->viewport_addr) & mask))
diff --git a/drivers/usb/ulpi/ulpi-viewport.c b/drivers/usb/ulpi/ulpi-viewport.c
index 3bb152be8939..55a62808384d 100644
--- a/drivers/usb/ulpi/ulpi-viewport.c
+++ b/drivers/usb/ulpi/ulpi-viewport.c
@@ -34,7 +34,7 @@
*/
static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
{
- int timeout = CONFIG_USB_ULPI_TIMEOUT;
+ int timeout = CFG_USB_ULPI_TIMEOUT;
/* Wait for the bits in mask to become zero. */
while (--timeout) {
diff --git a/drivers/usb/ulpi/ulpi.c b/drivers/usb/ulpi/ulpi.c
index dd0da0e841e5..b5d2c2c2d1c3 100644
--- a/drivers/usb/ulpi/ulpi.c
+++ b/drivers/usb/ulpi/ulpi.c
@@ -207,7 +207,7 @@ int ulpi_suspend(struct ulpi_viewport *ulpi_vp)
static int __ulpi_reset_wait(struct ulpi_viewport *ulpi_vp)
{
u32 val;
- int timeout = CONFIG_USB_ULPI_TIMEOUT;
+ int timeout = CFG_USB_ULPI_TIMEOUT;
/* Wait for the RESET bit to become zero */
while (--timeout) {
diff --git a/include/command.h b/include/command.h
index 966fd23c639f..d58b6101a89a 100644
--- a/include/command.h
+++ b/include/command.h
@@ -18,8 +18,8 @@
#endif
/* Default to a width of 8 characters for help message command width */
-#ifndef CONFIG_SYS_HELP_CMD_WIDTH
-#define CONFIG_SYS_HELP_CMD_WIDTH 10
+#ifndef CFG_SYS_HELP_CMD_WIDTH
+#define CFG_SYS_HELP_CMD_WIDTH 10
#endif
#ifndef __ASSEMBLY__
diff --git a/include/env_callback.h b/include/env_callback.h
index 85e7fe25f8fe..a9a14f2a84a5 100644
--- a/include/env_callback.h
+++ b/include/env_callback.h
@@ -14,8 +14,8 @@
#define ENV_CALLBACK_VAR ".callbacks"
/* Board configs can define additional static callback bindings */
-#ifndef CONFIG_ENV_CALLBACK_LIST_STATIC
-#define CONFIG_ENV_CALLBACK_LIST_STATIC
+#ifndef CFG_ENV_CALLBACK_LIST_STATIC
+#define CFG_ENV_CALLBACK_LIST_STATIC
#endif
#ifdef CONFIG_SILENT_CONSOLE
@@ -80,7 +80,7 @@
SILENT_CALLBACK \
"stdin:console,stdout:console,stderr:console," \
"serial#:serialno," \
- CONFIG_ENV_CALLBACK_LIST_STATIC
+ CFG_ENV_CALLBACK_LIST_STATIC
#ifndef CONFIG_SPL_BUILD
void env_callback_init(struct env_entry *var_entry);
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 6012a449fd23..8b133e703b40 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -51,18 +51,18 @@ enum fm_eth_type {
*/
#ifdef CONFIG_SYS_FMAN_V3
#ifdef CONFIG_TARGET_LS1046AFRWY
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CFG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#else
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
+#define CFG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
#endif
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CFG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CFG_SYS_NUM_FMAN == 2)
-#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
-#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
+#define CFG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CFG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
#endif
#else
-#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
+#define CFG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
+#define CFG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
#endif
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
@@ -77,7 +77,7 @@ enum fm_eth_type {
#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_1G_E, \
@@ -91,7 +91,7 @@ enum fm_eth_type {
#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
@@ -105,7 +105,7 @@ enum fm_eth_type {
#if (CFG_SYS_NUM_FMAN == 2)
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM2_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
@@ -118,7 +118,7 @@ enum fm_eth_type {
#else
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
@@ -134,7 +134,7 @@ enum fm_eth_type {
#if (CFG_SYS_NUM_FM1_10GEC >= 3)
#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
@@ -149,7 +149,7 @@ enum fm_eth_type {
#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_DTSEC1_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_1G_E, \
@@ -162,7 +162,7 @@ enum fm_eth_type {
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
- FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ FM_ETH_INFO_INITIALIZER(idx, CFG_SYS_FM1_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index a7272e4be705..c43f780e4cd1 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -48,25 +48,25 @@
#if defined(CONFIG_SYS_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
+#ifndef CFG_FSL_SDRAM_TYPE
+#define CFG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_SYS_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
+#ifndef CFG_FSL_SDRAM_TYPE
+#define CFG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_SYS_FSL_DDR3)
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
+#ifndef CFG_FSL_SDRAM_TYPE
+#define CFG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
#elif defined(CONFIG_SYS_FSL_DDR4)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
-#ifndef CONFIG_FSL_SDRAM_TYPE
-#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
+#ifndef CFG_FSL_SDRAM_TYPE
+#define CFG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
#endif
#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index a37a6e51b6f1..1abd1e5e57a8 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -40,21 +40,21 @@ struct ccsr_usb_phy {
u8 res_dc[0x334];
};
-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CFG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CFG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CFG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
-#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
+#define CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
+#define CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
+#define CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
#endif
-#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
-#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
-#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+#define CFG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CFG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CFG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
#define INC_DCNT_THRESHOLD_25MV (0 << 4)
#define INC_DCNT_THRESHOLD_50MV (1 << 4)
@@ -71,14 +71,14 @@ struct ccsr_usb_phy {
u32 usb_enable_override;
u8 res[0xe4];
};
-#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
-#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
-#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
-#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
-#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
-#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
-#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
+#define CFG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CFG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CFG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
#endif
/* USB Erratum Checking code */
diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h
index 71642d257b67..126623cf9a82 100644
--- a/include/usb/ulpi.h
+++ b/include/usb/ulpi.h
@@ -20,8 +20,8 @@
#define ULPI_ERROR (1 << 8) /* overflow from any register value */
-#ifndef CONFIG_USB_ULPI_TIMEOUT
-#define CONFIG_USB_ULPI_TIMEOUT 1000 /* timeout in us */
+#ifndef CFG_USB_ULPI_TIMEOUT
+#define CFG_USB_ULPI_TIMEOUT 1000 /* timeout in us */
#endif
/*
diff --git a/lib/gzip.c b/lib/gzip.c
index c6c0ec880cfb..2595b2d04b42 100644
--- a/lib/gzip.c
+++ b/lib/gzip.c
@@ -14,8 +14,8 @@
#include <u-boot/zlib.h>
#include "zlib/zutil.h"
-#ifndef CONFIG_GZIP_COMPRESS_DEF_SZ
-#define CONFIG_GZIP_COMPRESS_DEF_SZ 0x200
+#ifndef CFG_GZIP_COMPRESS_DEF_SZ
+#define CFG_GZIP_COMPRESS_DEF_SZ 0x200
#endif
#define ZALLOC_ALIGNMENT 16
@@ -75,17 +75,17 @@ int zzip(void *dst, unsigned long *lenp, unsigned char *src,
}
while (srclen > 0) {
- comp_len = (srclen > CONFIG_GZIP_COMPRESS_DEF_SZ) ?
- CONFIG_GZIP_COMPRESS_DEF_SZ : srclen;
+ comp_len = (srclen > CFG_GZIP_COMPRESS_DEF_SZ) ?
+ CFG_GZIP_COMPRESS_DEF_SZ : srclen;
s.next_in = src;
s.avail_in = comp_len;
- flush = (srclen > CONFIG_GZIP_COMPRESS_DEF_SZ)?
+ flush = (srclen > CFG_GZIP_COMPRESS_DEF_SZ)?
Z_NO_FLUSH : Z_FINISH;
do {
- left_len = (*lenp > CONFIG_GZIP_COMPRESS_DEF_SZ) ?
- CONFIG_GZIP_COMPRESS_DEF_SZ : *lenp;
+ left_len = (*lenp > CFG_GZIP_COMPRESS_DEF_SZ) ?
+ CFG_GZIP_COMPRESS_DEF_SZ : *lenp;
s.next_out = dst;
s.avail_out = left_len;
r = deflate(&s, flush);
diff --git a/lib/time.c b/lib/time.c
index 82350260eac4..42d15faf3758 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -19,8 +19,8 @@
#include <asm/io.h>
#include <linux/delay.h>
-#ifndef CONFIG_WD_PERIOD
-# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */
+#ifndef CFG_WD_PERIOD
+# define CFG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -199,7 +199,7 @@ void udelay(unsigned long usec)
do {
schedule();
- kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
+ kv = usec > CFG_WD_PERIOD ? CFG_WD_PERIOD : usec;
__udelay(kv);
usec -= kv;
} while(usec);
diff --git a/net/bootp.c b/net/bootp.c
index 7ac0093945c1..cae041988db2 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -44,15 +44,15 @@
#define PORT_BOOTPS 67 /* BOOTP server UDP port */
#define PORT_BOOTPC 68 /* BOOTP client UDP port */
-#ifndef CONFIG_DHCP_MIN_EXT_LEN /* minimal length of extension list */
-#define CONFIG_DHCP_MIN_EXT_LEN 64
+#ifndef CFG_DHCP_MIN_EXT_LEN /* minimal length of extension list */
+#define CFG_DHCP_MIN_EXT_LEN 64
#endif
-#ifndef CONFIG_BOOTP_ID_CACHE_SIZE
-#define CONFIG_BOOTP_ID_CACHE_SIZE 4
+#ifndef CFG_BOOTP_ID_CACHE_SIZE
+#define CFG_BOOTP_ID_CACHE_SIZE 4
#endif
-u32 bootp_ids[CONFIG_BOOTP_ID_CACHE_SIZE];
+u32 bootp_ids[CFG_BOOTP_ID_CACHE_SIZE];
unsigned int bootp_num_ids;
int bootp_try;
ulong bootp_start;
@@ -611,8 +611,8 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
*e++ = 255; /* End of the list */
/* Pad to minimal length */
-#ifdef CONFIG_DHCP_MIN_EXT_LEN
- while ((e - start) < CONFIG_DHCP_MIN_EXT_LEN)
+#ifdef CFG_DHCP_MIN_EXT_LEN
+ while ((e - start) < CFG_DHCP_MIN_EXT_LEN)
*e++ = 0;
#endif
--
2.25.1
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