[PATCH v3 1/2] serial: mxc: Wait for TX completion before reset

[Loic Poulain]

On Wed, 11 Jan 2023 at 09:08, Pali Rohár <pali at kernel.org> wrote:
>
> On Wednesday 11 January 2023 08:53:30 Loic Poulain wrote:
> > On Wed, 11 Jan 2023 at 00:53, Pali Rohár <pali at kernel.org> wrote:
> > >
> > > On Tuesday 10 January 2023 20:24:06 Loic Poulain wrote:
> > > > The u-boot console may show some corrupted characters when
> > > > printing in board_init() due to reset of the UART (probe)
> > > > before the TX FIFO has been completely drained.
> > > >
> > > > To fix this issue, and in case UART is still running, we now
> > > > try to flush the FIFO before proceeding to UART reinitialization.
> > > > For this we're waiting for Transmitter Complete bit, indicating
> > > > that the FIFO and the shift register are empty.
> > > >
> > > > flushing has a 4ms timeout guard, which is normally more than
> > > > enough to consume the FIFO @ low baudrate (9600bps).
> > > >
> > > > Signed-off-by: Loic Poulain <loic.poulain at linaro.org>
> > > > Tested-by: Lothar Waßmann <LW at KARO-electronics.de>
> > >
> > > Hello! Last time when I looked at this driver I was in impression that
> > > also _mxc_serial_setbrg() function requires calling some flush function
> > > at the beginning. Could you please check if it is needed or not? I'm
> > > really not sure.
> >
> > _mxc_serial_setbrg is usually called after init, which now includes that flush.
>
> I'm looking at it and this function is called also from
> mxc_serial_setbrg() callback, which is used by u-boot to change baudrate
> after the init.

Ok, good point, then it makes sense to add this guard here as well.