[PATCH] net: zynq_gem: Add a 10ms delay in zynq_gem_init()
harini.katakam at amd.com
Wed Jan 11 12:20:55 CET 2023
> -----Original Message-----
> From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Stefan Roese
> Sent: Wednesday, January 11, 2023 1:01 PM
> To: u-boot at lists.denx.de
> Cc: Michal Simek <michal.simek at amd.com>; Ramon Fried
> <rfried.dev at gmail.com>; Sean Anderson <sean.anderson at seco.com>
> Subject: [PATCH] net: zynq_gem: Add a 10ms delay in zynq_gem_init()
> In our system using ZynqMP with an external SGMII PHY it's necessary to
> wait a short while after the configuration in zynq_gem_init() before the xfer
> starts. Otherwise the first packet(s) might get dropped, resulting in a delay at
> the start of the ethernet transfers.
> This patch adds a minimal delay of 10ms which fixes problems of dropped
> first packages.
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Michal Simek <michal.simek at amd.com>
> Cc: Ramon Fried <rfried.dev at gmail.com>
> Cc: Sean Anderson <sean.anderson at seco.com>
> drivers/net/zynq_gem.c | 7 +++++++
> 1 file changed, 7 insertions(+)
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
> 507b19b75975..26e468766871 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -522,6 +522,13 @@ static int zynq_gem_init(struct udevice *dev)
> return ret;
> + /*
> + * Some additional minimal delay seems to be needed so that
> + * the first packet will be sent correctly
> + */
> + mdelay(10);
Thanks for the patch. The PCS status check in your v1 seems valid.
However, this delay of 10 msecs should not be necessary. If the PCS
status (when autoneg is enabled with the external PHY on your board)
shows link up, that's enough. Could you please consider the following
to investigate why initial packets are lost?
-> If the external PHY on your board has a hardware reset please
consider updating the reset-assert-us and reset-deassert-us properties
to ensure PHY is ready before access.
-> Can you please check if there's any link stability issues in the initial
msecs? Monitoring the serdes/GTR SGMII lane that's setup on ZynqMP
will be useful.
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