[PATCH 9/9] arm64: imx8mp: Drop EQoS GPR[1] board workaround

Marek Vasut marex at denx.de
Thu Jan 19 22:44:53 CET 2023


The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut <marex at denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro at collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin at leica-geosystems.com>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Joe Hershberger <joe.hershberger at ni.com>
Cc: Lukasz Majewski <lukma at denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler at toradex.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Michael Trimarchi <michael at amarulasolutions.com>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Ramon Fried <rfried.dev at gmail.com>
Cc: Sean Anderson <seanga2 at gmail.com>
Cc: Stefano Babic <sbabic at denx.de>
Cc: Tim Harvey <tharvey at gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai at amarulasolutions.com>
Cc: u-boot at lists.denx.de
---
 .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c         | 17 +----------------
 .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 14 --------------
 board/engicam/imx8mp/icore_mx8mp.c              | 16 ----------------
 board/freescale/imx8mp_evk/imx8mp_evk.c         | 17 -----------------
 board/gateworks/venice/venice.c                 | 15 ---------------
 board/msc/sm2s_imx8mp/sm2s_imx8mp.c             | 15 ---------------
 board/toradex/verdin-imx8mp/verdin-imx8mp.c     | 16 ----------------
 7 files changed, 1 insertion(+), 109 deletions(-)

diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index aa9687f7a9d..4c3fb6cbe35 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -113,7 +113,7 @@ static const iomux_v3_cfg_t eqos_rst_pads[] = {
 	MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static void setup_iomux_eqos(void)
+static int setup_eqos(void)
 {
 	imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
 					 ARRAY_SIZE(eqos_rst_pads));
@@ -124,21 +124,6 @@ static void setup_iomux_eqos(void)
 	gpio_direction_output(EQOS_RST_PAD, 1);
 	mdelay(100);
 }
-
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	setup_iomux_eqos();
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
 #endif /* CONFIG_DWC_ETH_QOS */
 
 int board_phy_config(struct phy_device *phydev)
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index e83dd52c3a6..319ea6e93c5 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -37,19 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
 	return 0;
 }
 
-static void setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* Set INTF as RGMII, enable RGMII TXC clock. */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	set_clk_eqos(ENET_125MHZ);
-}
-
 static void setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
@@ -128,7 +115,6 @@ int dh_setup_mac_address(void)
 
 int board_init(void)
 {
-	setup_eqos();
 	setup_fec();
 	return 0;
 }
diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c
index b309a12df08..b80513c7957 100644
--- a/board/engicam/imx8mp/icore_mx8mp.c
+++ b/board/engicam/imx8mp/icore_mx8mp.c
@@ -34,19 +34,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if CONFIG_IS_ENABLED(NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -61,9 +48,6 @@ int board_init(void)
 	if (CONFIG_IS_ENABLED(FEC_MXC))
 		setup_fec();
 
-	if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
-		setup_eqos();
-
 	return 0;
 }
 
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 8971a827df3..0fefdafadfa 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -29,19 +29,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if CONFIG_IS_ENABLED(NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -59,10 +46,6 @@ int board_init(void)
 		setup_fec();
 	}
 
-	if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
-		ret = setup_eqos();
-	}
-
 	return ret;
 }
 
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index c4d86c26a9b..bc8937b366c 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -58,19 +58,6 @@ static int setup_fec(void)
 	return 0;
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 	unsigned short val;
@@ -115,8 +102,6 @@ int board_init(void)
 
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
-	if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
-		setup_eqos();
 
 	return 0;
 }
diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
index 3913c4f2427..6ccbf02db06 100644
--- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
+++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
@@ -30,19 +30,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 	if (phydev->drv->config)
@@ -54,7 +41,5 @@ int board_init(void)
 {
 	setup_fec();
 
-	setup_eqos();
-
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index 9c2e44a1229..5490d3ed44a 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -49,19 +49,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if IS_ENABLED(CONFIG_NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -78,9 +65,6 @@ int board_init(void)
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
 
-	if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
-		ret = setup_eqos();
-
 	return ret;
 }
 
-- 
2.39.0



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