[PATCH v1 06/17] clk: starfive: Add StarFive JH7110 clock driver

[Sean Anderson]

On 1/9/23 04:31, yanhong wang wrote:
> On 2023/1/5 3:13, Sean Anderson wrote:
>> On 12/11/22 21:50, Yanhong Wang wrote:
>>> +static const struct starfive_pllx_rate jh7110_pll2_tbl[] = {
>>> +    PLLX_RATE(1228800000UL, 15, 768, 1, 1, 1),
>>> +    PLLX_RATE(1188000000UL, 2, 99, 1, 1, 1),
>>> +};
>>
>> All of these rates set postdiv1/dacpd/dsmpd to 1. Do these fields need
>> to be stored?
>>
> The PLL supports integer and fraction muligple, you should set dacpd and dsmpd to high while integer multiple mode,
> and set both them to low while fraction multiple mode. The default configration set to integer multiple mode.
> 
> Integer Multiple Mode
> 
> Both dacpd and dsmpd should be set as 1 while integer multiple mode.
> 
> The frequency of outputs can be figured out as below.
> 
>              Fvco = Fref*Nl/M
> NI is integer frequency dividing ratio of feedback divider, set by fbdiv1[11:0] , NI = 8, 9, 10, 12.13....4095
> M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
> 
>             Fclko1 = Fvco/Q1
> Q1 is frequency dividing ratio of post divider, set by postdiv1[1:0],Q1= 1,2,4,8
> 
> 
> Fraction Multiple Mode
> 
> Both dacpd and dsmpd should be set as 0 while integer multiple mode.
> 
>             Fvco = Fref*(NI+NE)/M
> NI is integer frequency dividing ratio of feedback divider, set by fbdiv[11:0] , NI = 8, 9, 10, 12.13....4095
> NF is fractional frequency dividing ratio, set by frac[23:0],  NF =frac[23:0]/2^24= 0~0.99999994
> M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
> 
>            Fclko1 = Fvco/Q1
> Q1 is frequency dividing ratio of post divider, set by postdivl[1:0],Q1= 1,24,8
> 

If you are going to set these to the same value every time you can omit them
from struct starfive_pllx_rate.

--Sean