[PATCH v2 16/17] riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree
Sean Anderson
seanga2 at gmail.com
Sat Jan 21 19:46:50 CET 2023
On 1/18/23 03:11, Yanhong Wang wrote:
> Add initial device tree for StarFive VisionFive v2 board.
>
> Signed-off-by: Yanhong Wang <yanhong.wang at starfivetech.com>
> ---
> arch/riscv/dts/Makefile | 2 +-
> .../dts/starfive_visionfive2-u-boot.dtsi | 84 +++++++
> arch/riscv/dts/starfive_visionfive2.dts | 234 ++++++++++++++++++
> 3 files changed, 319 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
> create mode 100644 arch/riscv/dts/starfive_visionfive2.dts
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 5c15a0f303..0351cc0c38 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -7,7 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
> dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> -
> +dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
> include $(srctree)/scripts/Makefile.dts
>
> targets += $(dtb-y)
> diff --git a/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
> new file mode 100644
> index 0000000000..1b4e3392ab
> --- /dev/null
> +++ b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include "binman.dtsi"
> +#include "jh7110-u-boot.dtsi"
> +/ {
> + chosen {
> + u-boot,dm-spl;
> + };
> +
> + firmware {
> + spi0 = &qspi;
> + u-boot,dm-spl;
> + };
> +
> + config {
> + u-boot,dm-spl;
> + u-boot,spl-payload-offset = <0x100000>;
> + };
> +
> + memory at 40000000 {
> + u-boot,dm-spl;
> + };
> +
> + soc {
> + u-boot,dm-spl;
> +
> + dmc: dmc at 15700000 {
> + u-boot,dm-spl;
> + compatible = "starfive,jh7110-dmc";
> + reg = <0x0 0x15700000 0x0 0x10000>,
> + <0x0 0x13000000 0x0 0x10000>;
> + resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> + <&syscrg JH7110_SYSRST_DDR_OSC>,
> + <&syscrg JH7110_SYSRST_DDR_APB>;
> + reset-names = "axi", "osc", "apb";
> + clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
> + clock-names = "pll1";
> + clock-frequency = <2133>;
> + };
Again, needs to go in SoC dtsi.
Here are the rules for where something should go:
- If it is part of the chip, it goes in the SoC dtsi, even if it is not always
used! You can disable it by default (status = "disabled") if this is the case.
- If it is on the board, it goes in the board dts.
- If it is a property which is added to a node to support a board peripheral,
it goes in the board dts.
- If it is a U-Boot-specific property, it goes in the -u-boot.dts[i]
--Sean
> + };
> +};
> +
> +&sys_syscon {
> + u-boot,dm-spl;
> +};
> +
> +&uart0 {
> + u-boot,dm-spl;
> +};
> +
> +&sdio0 {
> + u-boot,dm-spl;
> +};
> +
> +&sdio1 {
> + u-boot,dm-spl;
> +};
> +
> +&qspi {
> + u-boot,dm-spl;
> +
> + nor-flash at 0 {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&osc {
> + u-boot,dm-spl;
> +};
> +
> +&aoncrg {
> + u-boot,dm-spl;
> +};
> +
> +&syscrg {
> + u-boot,dm-spl;
> +};
> +
> +&stgcrg {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
> new file mode 100644
> index 0000000000..52b31546da
> --- /dev/null
> +++ b/arch/riscv/dts/starfive_visionfive2.dts
> @@ -0,0 +1,234 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "jh7110.dtsi"
> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "StarFive VisionFive V2";
> + compatible = "starfive,jh7110";
> +
> + aliases {
> + spi0 = &qspi;
> + mmc0 = &sdio0;
> + mmc1 = &sdio1;
> + };
> +
> + chosen {
> + stdout-path = "/soc/serial at 10000000:115200";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory at 40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + soc {
> + sys_syscon: sys_syscon at 13030000 {
> + compatible = "syscon";
> + reg = <0x0 0x13030000 0x0 0x1000>;
> + };
> + };
ditto
> +};
> +
> +&S76_0 {
> + status = "okay";
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&clk_rtc {
> + clock-frequency = <32768>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&gpio {
> + status = "okay";
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> + GPOEN_ENABLE, GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW,
> + GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
> + bias-pull-up;
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +
> + mmc0_pins: mmc0-pins {
> + mmc0-pins-rest {
> + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> + GPOEN_ENABLE, GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> + sdcard1_pins: sdcard1-pins {
> + sdcard1-pins0 {
> + pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> + GPOEN_ENABLE, GPI_NONE)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + sdcard1-pins1 {
> + pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> + GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> +
> + sdcard1-pins2 {
> + pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> + GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> +
> + sdcard1-pins3 {
> + pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> + GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> +
> + sdcard1-pins4 {
> + pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> + GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> +
> + sdcard1-pins5 {
> + pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> + GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
> + bias-pull-up;
> + drive-strength = <12>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> +
> +&sdio0 {
> + bus-width = <8>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "okay";
> +};
> +
> +&sdio1 {
> + bus-width = <4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdcard1_pins>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + reg-offset = <0>;
> + current-speed = <115200>;
> + clock-frequency = <24000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&qspi {
> + spi-max-frequency = <250000000>;
> + status = "okay";
> +
> + nor-flash at 0 {
> + compatible = "jedec,spi-nor";
> + reg=<0>;
> + spi-max-frequency = <100000000>;
> + cdns,tshsl-ns = <1>;
> + cdns,tsd2d-ns = <1>;
> + cdns,tchsh-ns = <1>;
> + cdns,tslch-ns = <1>;
> + };
> +};
> +
> +&syscrg {
> + starfive,sys-syscon = <&sys_syscon>;
> +};
ditto
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