[PATCH 31/41] ddr: imx8m: Fix DDR inline ECC scruber configuration

[Peng Fan (OSS)]

From: Ye Li <ye.li at nxp.com>

The ECC scruber setting is incorrect and decreases the DDR performance
in ECC enabled mode.

Detail changes:
-Before, scrub_burst was 0; this is not allowed per SNPS umctl2 spec.
 Set to "2" to align with DXL whichw as found to be most optimal setting
-Before, scrub_interval was set to 1, which means back-to-back scrubber
 reads will occur very frequently, potentially effecting performance.
-Set scrub_interval to 0xFF which is the default value. However, users
 can tune this to meet their system needs.

Reviewed-by: Peng Fan <peng.fan at nxp.com>
Signed-off-by: Ye Li <ye.li at nxp.com>
Signed-off-by: Oliver Chen <oliver.chen at nxp.com>
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 drivers/ddr/imx/imx8m/ddr_init.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index 52a4aa63230..182a11484ca 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -59,9 +59,9 @@ void ddrc_inline_ecc_scrub(unsigned int start_address,
 	/* Step11: Disable SBR by programming SBRCTL.scrub_en=0 */
 	clrbits_le32(DDRC_SBRCTL(0), 0x1);
 	/* Step12: Prepare for normal scrub operation(Read) and set scrub_interval*/
-	reg32_write(DDRC_SBRCTL(0), 0x100);
+	reg32_write(DDRC_SBRCTL(0), 0xFF20);
 	/* Step13: Enable the SBR by programming SBRCTL.scrub_en=1 */
-	reg32_write(DDRC_SBRCTL(0), 0x101);
+	reg32_write(DDRC_SBRCTL(0), 0xFF21);
 	/* Step14: Enable AXI ports by programming */
 	reg32_write(DDRC_PCTRL_0(0), 0x1);
 	/* Step15: Disable quasi-dynamic programming */
-- 
2.36.0