[PATCH 2/7] rockchip: Add rk3588 core architecture
fatorangecat at 189.cn
fatorangecat at 189.cn
Tue Jan 24 20:13:06 CET 2023
From: Joseph Chen <chenjh at rock-chips.com>
RK3588 is a high-performance and low power octa-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen <chenjh at rock-chips.com>
---
arch/arm/include/asm/arch-rk3588/boot0.h | 11 +
arch/arm/include/asm/arch-rk3588/gpio.h | 11 +
arch/arm/include/asm/arch-rockchip/clock.h | 7 +
.../include/asm/arch-rockchip/grf_rk3588.h | 182 ++++++++++
.../include/asm/arch-rockchip/ioc_rk3588.h | 102 ++++++
arch/arm/mach-rockchip/Kconfig | 22 ++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3588/Kconfig | 32 ++
arch/arm/mach-rockchip/rk3588/Makefile | 9 +
arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 41 +++
arch/arm/mach-rockchip/rk3588/rk3588.c | 330 ++++++++++++++++++
arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 31 ++
include/configs/rk3588_common.h | 37 ++
13 files changed, 816 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3588.h
create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c
create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
create mode 100644 include/configs/rk3588_common.h
diff --git a/arch/arm/include/asm/arch-rk3588/boot0.h b/arch/arm/include/asm/arch-rk3588/boot0.h
new file mode 100644
index 0000000000..dea2b20252
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3588/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3588/gpio.h b/arch/arm/include/asm/arch-rk3588/gpio.h
new file mode 100644
index 0000000000..b48c0a5cf8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3588/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 566bdcc4fa..52eaf6f5e4 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -22,6 +22,13 @@ enum {
ROCKCHIP_SYSCON_PMUSGRF,
ROCKCHIP_SYSCON_CIC,
ROCKCHIP_SYSCON_MSCH,
+ ROCKCHIP_SYSCON_PCIE30_PHY_GRF,
+ ROCKCHIP_SYSCON_PHP_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY0_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY1_GRF,
+ ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
+ ROCKCHIP_SYSCON_VOP_GRF,
+ ROCKCHIP_SYSCON_VO_GRF,
};
/* Standard Rockchip clock numbers */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
new file mode 100644
index 0000000000..51152974b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3588_H
+#define _ASM_ARCH_GRF_RK3588_H
+
+struct rk3588_sys_grf {
+ u32 wdt_con0; /* Address Offset: 0x0000 */
+ u32 reserved0004[3]; /* Address Offset: 0x0004 */
+ u32 uart_con0; /* Address Offset: 0x0010 */
+ u32 uart_con1; /* Address Offset: 0x0014 */
+ u32 reserved0018[42]; /* Address Offset: 0x0018 */
+ u32 gic_con0; /* Address Offset: 0x00C0 */
+ u32 reserved00c4[79]; /* Address Offset: 0x00C4 */
+ u32 memcfg_con0; /* Address Offset: 0x0200 */
+ u32 memcfg_con1; /* Address Offset: 0x0204 */
+ u32 memcfg_con2; /* Address Offset: 0x0208 */
+ u32 memcfg_con3; /* Address Offset: 0x020C */
+ u32 memcfg_con4; /* Address Offset: 0x0210 */
+ u32 memcfg_con5; /* Address Offset: 0x0214 */
+ u32 memcfg_con6; /* Address Offset: 0x0218 */
+ u32 memcfg_con7; /* Address Offset: 0x021C */
+ u32 memcfg_con8; /* Address Offset: 0x0220 */
+ u32 memcfg_con9; /* Address Offset: 0x0224 */
+ u32 memcfg_con10; /* Address Offset: 0x0228 */
+ u32 memcfg_con11; /* Address Offset: 0x022C */
+ u32 memcfg_con12; /* Address Offset: 0x0230 */
+ u32 memcfg_con13; /* Address Offset: 0x0234 */
+ u32 memcfg_con14; /* Address Offset: 0x0238 */
+ u32 memcfg_con15; /* Address Offset: 0x023C */
+ u32 memcfg_con16; /* Address Offset: 0x0240 */
+ u32 memcfg_con17; /* Address Offset: 0x0244 */
+ u32 memcfg_con18; /* Address Offset: 0x0248 */
+ u32 memcfg_con19; /* Address Offset: 0x024C */
+ u32 memcfg_con20; /* Address Offset: 0x0250 */
+ u32 memcfg_con21; /* Address Offset: 0x0254 */
+ u32 memcfg_con22; /* Address Offset: 0x0258 */
+ u32 memcfg_con23; /* Address Offset: 0x025C */
+ u32 memcfg_con24; /* Address Offset: 0x0260 */
+ u32 reserved0264; /* Address Offset: 0x0264 */
+ u32 memcfg_con26; /* Address Offset: 0x0268 */
+ u32 memcfg_con27; /* Address Offset: 0x026C */
+ u32 memcfg_con28; /* Address Offset: 0x0270 */
+ u32 memcfg_con29; /* Address Offset: 0x0274 */
+ u32 memcfg_con30; /* Address Offset: 0x0278 */
+ u32 memcfg_con31; /* Address Offset: 0x027C */
+ u32 reserved0280[33]; /* Address Offset: 0x0280 */
+ u32 soc_con1; /* Address Offset: 0x0304 */
+ u32 soc_con2; /* Address Offset: 0x0308 */
+ u32 soc_con3; /* Address Offset: 0x030C */
+ u32 reserved0310[2]; /* Address Offset: 0x0310 */
+ u32 soc_con6; /* Address Offset: 0x0318 */
+ u32 soc_con7; /* Address Offset: 0x031C */
+ u32 soc_con8; /* Address Offset: 0x0320 */
+ u32 soc_con9; /* Address Offset: 0x0324 */
+ u32 soc_con10; /* Address Offset: 0x0328 */
+ u32 soc_con11; /* Address Offset: 0x032C */
+ u32 soc_con12; /* Address Offset: 0x0330 */
+ u32 soc_con13; /* Address Offset: 0x0334 */
+ u32 reserved0338[18]; /* Address Offset: 0x0338 */
+ u32 soc_status0; /* Address Offset: 0x0380 */
+ u32 soc_status1; /* Address Offset: 0x0384 */
+ u32 soc_status2; /* Address Offset: 0x0388 */
+ u32 soc_status3; /* Address Offset: 0x038C */
+ u32 reserved0390[92]; /* Address Offset: 0x0390 */
+ u32 otp_key08; /* Address Offset: 0x0500 */
+ u32 otp_key0d; /* Address Offset: 0x0504 */
+ u32 otp_key0e; /* Address Offset: 0x0508 */
+ u32 reserved050c[61]; /* Address Offset: 0x050C */
+ u32 chip_id; /* Address Offset: 0x0600 */
+};
+
+check_member(rk3588_sys_grf, chip_id, 0x0600);
+
+struct rk3588_php_grf {
+ u32 php_con0; /* Address Offset: 0x0000 */
+ u32 php_con1; /* Address Offset: 0x0004 */
+ u32 gmac_con0; /* Address Offset: 0x0008 */
+ u32 reserved000c; /* Address Offset: 0x000C */
+ u32 sata_con0; /* Address Offset: 0x0010 */
+ u32 sata_con1; /* Address Offset: 0x0014 */
+ u32 sata_con2; /* Address Offset: 0x0018 */
+ u32 php_mmu_con0; /* Address Offset: 0x001C */
+ u32 php_mmu_con1; /* Address Offset: 0x0020 */
+ u32 php_mmu_con2; /* Address Offset: 0x0024 */
+ u32 its_taddr0; /* Address Offset: 0x0028 */
+ u32 its_taddr1; /* Address Offset: 0x002C */
+ u32 pcie_mmu_pciemode; /* Address Offset: 0x0030 */
+ u32 pcie_mmu_con0; /* Address Offset: 0x0034 */
+ u32 pcie_mmu_con1; /* Address Offset: 0x0038 */
+ u32 pcie_mmu_con2; /* Address Offset: 0x003C */
+ u32 mem_con0; /* Address Offset: 0x0040 */
+ u32 php_st0; /* Address Offset: 0x0044 */
+ u32 php_st1; /* Address Offset: 0x0048 */
+ u32 php_st2; /* Address Offset: 0x004C */
+ u32 php_st3; /* Address Offset: 0x0050 */
+ u32 php_st4; /* Address Offset: 0x0054 */
+ u32 mmu_pmu_ack; /* Address Offset: 0x0058 */
+ u32 pcie_mmu_con6; /* Address Offset: 0x005C */
+ u32 pcie_mmu_con7; /* Address Offset: 0x0060 */
+ u32 mem_con5; /* Address Offset: 0x0064 */
+ u32 mem_con10; /* Address Offset: 0x0068 */
+ u32 reserved006c; /* Address Offset: 0x006C */
+ u32 clk_con1; /* Address Offset: 0x0070 */
+ u32 gmac0_sid_aw; /* Address Offset: 0x0074 */
+ u32 gmac0_ssid_aw; /* Address Offset: 0x0078 */
+ u32 gmac1_sid_aw; /* Address Offset: 0x007C */
+ u32 gmac1_ssid_aw; /* Address Offset: 0x0080 */
+ u32 sata0_sid_aw; /* Address Offset: 0x0084 */
+ u32 sata0_ssid_aw; /* Address Offset: 0x0088 */
+ u32 sata1_sid_aw; /* Address Offset: 0x008C */
+ u32 sata1_ssid_aw; /* Address Offset: 0x0090 */
+ u32 sata2_sid_aw; /* Address Offset: 0x0094 */
+ u32 sata2_ssid_aw; /* Address Offset: 0x0098 */
+ u32 gmac0_sid_ar; /* Address Offset: 0x009C */
+ u32 gmac0_ssid_ar; /* Address Offset: 0x00A0 */
+ u32 gmac1_sid_ar; /* Address Offset: 0x00A4 */
+ u32 gmac1_ssid_ar; /* Address Offset: 0x00A8 */
+ u32 sata0_sid_ar; /* Address Offset: 0x00AC */
+ u32 sata0_ssid_ar; /* Address Offset: 0x00B0 */
+ u32 sata1_sid_ar; /* Address Offset: 0x00B4 */
+ u32 sata1_ssid_ar; /* Address Offset: 0x00B8 */
+ u32 sata2_sid_ar; /* Address Offset: 0x00BC */
+ u32 sata2_ssid_ar; /* Address Offset: 0x00C0 */
+ u32 usb3otg_2_sid_ar; /* Address Offset: 0x00C4 */
+ u32 usb3otg_2_ssid_ar; /* Address Offset: 0x00C8 */
+ u32 usb3otg_2_sid_aw; /* Address Offset: 0x00CC */
+ u32 usb3otg_2_ssid_aw; /* Address Offset: 0x00D0 */
+ u32 gmac_con_pst; /* Address Offset: 0x00D4 */
+ u32 gmac0_cmd; /* Address Offset: 0x00D8 */
+ u32 gmac1_cmd; /* Address Offset: 0x00DC */
+ u32 mem_con11; /* Address Offset: 0x00E0 */
+ u32 usb3otg_2_con0; /* Address Offset: 0x00E4 */
+ u32 usb3otg_2_con1; /* Address Offset: 0x00E8 */
+ u32 usb3otg_2_intcon; /* Address Offset: 0x00EC */
+ u32 usb3otg_2_st_lat0; /* Address Offset: 0x00F0 */
+ u32 usb3otg_2_st_lat1; /* Address Offset: 0x00F4 */
+ u32 usb3otg_2_st_cb; /* Address Offset: 0x00F8 */
+ u32 usb3otg_2_st; /* Address Offset: 0x00FC */
+ u32 pciesel_con; /* Address Offset: 0x0100 */
+ u32 utmi_con; /* Address Offset: 0x0104 */
+ u32 reserved0108; /* Address Offset: 0x0108 */
+ u32 pcie4l_sid_aw; /* Address Offset: 0x010C */
+ u32 pcie4l_sid_ar; /* Address Offset: 0x0110 */
+ u32 pcie2l_sid_aw; /* Address Offset: 0x0114 */
+ u32 pcie2l_sid_ar; /* Address Offset: 0x0118 */
+ u32 pcie1l0_sid_aw; /* Address Offset: 0x011C */
+ u32 pcie1l0_sid_ar; /* Address Offset: 0x0120 */
+ u32 pcie1l1_sid_aw; /* Address Offset: 0x0124 */
+ u32 pcie1l1_sid_ar; /* Address Offset: 0x0128 */
+ u32 pcie1l2_sid_aw; /* Address Offset: 0x012C */
+ u32 pcie1l2_sid_ar; /* Address Offset: 0x0130 */
+ u32 reserved0134; /* Address Offset: 0x0134 */
+ u32 pcie_ats; /* Address Offset: 0x0138 */
+ u32 st_utmi; /* Address Offset: 0x013C */
+ u32 reserved0140; /* Address Offset: 0x0140 */
+ u32 pcie4l_ssid_aw; /* Address Offset: 0x0144 */
+ u32 pcie4l_ssid_ar; /* Address Offset: 0x0148 */
+ u32 pcie2l_ssid_aw; /* Address Offset: 0x014C */
+ u32 pcie2l_ssid_ar; /* Address Offset: 0x0150 */
+ u32 pcie1l0_ssid_aw; /* Address Offset: 0x0154 */
+ u32 pcie1l0_ssid_ar; /* Address Offset: 0x0158 */
+ u32 pcie1l1_ssid_aw; /* Address Offset: 0x015C */
+ u32 pcie1l1_ssid_ar; /* Address Offset: 0x0160 */
+ u32 pcie1l2_ssid_aw; /* Address Offset: 0x0164 */
+ u32 pcie1l2_ssid_ar; /* Address Offset: 0x0168 */
+ u32 pcie_ssid_v; /* Address Offset: 0x016C */
+ u32 reserved0170; /* Address Offset: 0x0170 */
+ u32 sata_pd_sel; /* Address Offset: 0x0174 */
+ u32 pcie_mmu_irq_clr; /* Address Offset: 0x0178 */
+ u32 php_mmu_irq_clr; /* Address Offset: 0x017C */
+ u32 pcie_mmu_st; /* Address Offset: 0x0180 */
+ u32 php_mmu_st; /* Address Offset: 0x0184 */
+ u32 reserved0188; /* Address Offset: 0x0188 */
+ u32 php_st0b; /* Address Offset: 0x018C */
+};
+
+check_member(rk3588_php_grf, php_st0b, 0x018c);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
new file mode 100644
index 0000000000..9d8ebb9e63
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_IOC_RK3588_H
+#define _ASM_ARCH_IOC_RK3588_H
+
+struct rk3588_bus_ioc {
+ u32 reserved0000[3]; /* Address Offset: 0x0000 */
+ u32 gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
+ u32 gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
+ u32 gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
+ u32 gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
+ u32 gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
+ u32 gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
+ u32 gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
+ u32 gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
+ u32 gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
+ u32 gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
+ u32 gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
+ u32 gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
+ u32 gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
+ u32 gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
+ u32 gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
+ u32 gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
+ u32 gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
+ u32 gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
+ u32 gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
+ u32 gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
+ u32 gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
+ u32 gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
+ u32 gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
+ u32 gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
+ u32 gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
+ u32 gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
+ u32 gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
+ u32 gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
+ u32 gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
+ u32 gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
+ u32 gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
+ u32 gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
+ u32 gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
+ u32 gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
+ u32 gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
+ u32 gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
+ u32 gpio4d_iomux_sel_h; /* Address Offset: 0x009C */
+};
+
+check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+
+struct rk3588_pmu1_ioc {
+ u32 gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
+ u32 gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
+ u32 gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
+ u32 reserved0012; /* Address Offset: 0x000C */
+ u32 gpio0a_ds_l; /* Address Offset: 0x0010 */
+ u32 gpio0a_ds_h; /* Address Offset: 0x0014 */
+ u32 gpio0b_ds_l; /* Address Offset: 0x0018 */
+ u32 reserved0028; /* Address Offset: 0x001C */
+ u32 gpio0a_p; /* Address Offset: 0x0020 */
+ u32 gpio0b_p; /* Address Offset: 0x0024 */
+ u32 gpio0a_ie; /* Address Offset: 0x0028 */
+ u32 gpio0b_ie; /* Address Offset: 0x002C */
+ u32 gpio0a_smt; /* Address Offset: 0x0030 */
+ u32 gpio0b_smt; /* Address Offset: 0x0034 */
+ u32 gpio0a_pdis; /* Address Offset: 0x0038 */
+ u32 gpio0b_pdis; /* Address Offset: 0x003C */
+ u32 xin_con; /* Address Offset: 0x0040 */
+};
+
+check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+
+struct rk3588_pmu2_ioc {
+ u32 gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
+ u32 gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
+ u32 gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
+ u32 gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
+ u32 gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
+ u32 gpio0b_ds_h; /* Address Offset: 0x0014 */
+ u32 gpio0c_ds_l; /* Address Offset: 0x0018 */
+ u32 gpio0c_ds_h; /* Address Offset: 0x001C */
+ u32 gpio0d_ds_l; /* Address Offset: 0x0020 */
+ u32 gpio0d_ds_h; /* Address Offset: 0x0024 */
+ u32 gpio0b_p; /* Address Offset: 0x0028 */
+ u32 gpio0c_p; /* Address Offset: 0x002C */
+ u32 gpio0d_p; /* Address Offset: 0x0030 */
+ u32 gpio0b_ie; /* Address Offset: 0x0034 */
+ u32 gpio0c_ie; /* Address Offset: 0x0038 */
+ u32 gpio0d_ie; /* Address Offset: 0x003C */
+ u32 gpio0b_smt; /* Address Offset: 0x0040 */
+ u32 gpio0c_smt; /* Address Offset: 0x0044 */
+ u32 gpio0d_smt; /* Address Offset: 0x0048 */
+ u32 gpio0b_pdis; /* Address Offset: 0x004C */
+ u32 gpio0c_pdis; /* Address Offset: 0x0050 */
+ u32 gpio0d_pdis; /* Address Offset: 0x0054 */
+};
+
+check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054);
+
+#endif
+
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index b678ec4131..1137dad10a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -294,6 +294,27 @@ config ROCKCHIP_RK3568
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3588
+ bool "Support Rockchip RK3588"
+ select ARM64
+ select ARM_SMCCC
+ select CLK
+ select GICV3
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DEBUG_UART_BOARD_INIT
+ imply ROCKCHIP_COMMON_BOARD
+ help
+ The Rockchip RK3588 is a ARM-based SoC with a dual-core Cortex-A76
+ and quad-core Cortex-A55.
+ including NEON and GPU, 3MB L3 cache, Mali-G610 based graphics,
+ two video interfaces supporting HDMI and eDP, several DDR4 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@@ -491,6 +512,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
+source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 32138fa723..bee4fa4b5a 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
+obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
new file mode 100644
index 0000000000..7086efdc95
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -0,0 +1,32 @@
+if ROCKCHIP_RK3588
+
+config TARGET_EVB_RK3588
+ bool "RK3588 evaluation board"
+ select BOARD_LATE_INIT
+ help
+ RK3588 EVB is a evaluation board for Rockchp RK3588.
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xfd58a200
+
+config ROCKCHIP_STIMER_BASE
+ default 0xfd8c8000
+
+config SYS_SOC
+ default "rk3588"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xfdcc1000
+
+config TPL_MAX_SIZE
+ default 61440
+
+source "board/rockchip/evb_rk3588/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3588/Makefile b/arch/arm/mach-rockchip/rk3588/Makefile
new file mode 100644
index 0000000000..06239bea23
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2021 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk_rk3588.o
+obj-y += rk3588.o
+obj-y += syscon_rk3588.o
diff --git a/arch/arm/mach-rockchip/rk3588/clk_rk3588.c b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
new file mode 100644
index 0000000000..c896d0371a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/clk_rk3588.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3588_cru), devp);
+}
+
+#if (IS_ENABLED(CONFIG_CLK_SCMI))
+int rockchip_get_scmi_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(scmi_clock), devp);
+}
+#endif
+
+void *rockchip_get_cru(void)
+{
+ struct rk3588_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
new file mode 100644
index 0000000000..cfc0688891
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3588.h>
+#include <dt-bindings/clock/rk3588-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FIREWALL_DDR_BASE 0xfe030000
+#define FW_DDR_MST5_REG 0x54
+#define FW_DDR_MST13_REG 0x74
+#define FW_DDR_MST21_REG 0x94
+#define FW_DDR_MST26_REG 0xa8
+#define FW_DDR_MST27_REG 0xac
+#define FIREWALL_SYSMEM_BASE 0xfe038000
+#define FW_SYSM_MST5_REG 0x54
+#define FW_SYSM_MST13_REG 0x74
+#define FW_SYSM_MST21_REG 0x94
+#define FW_SYSM_MST26_REG 0xa8
+#define FW_SYSM_MST27_REG 0xac
+#define SYS_GRF_BASE 0xfd58c000
+#define SYS_GRF_SOC_CON6 0x0318
+#define USBGRF_BASE 0xfd5ac000
+#define USB_GRF_USB3OTG0_CON1 0x001c
+#define BUS_SGRF_BASE 0xfd586000
+#define BUS_SGRF_FIREWALL_CON18 0x288
+#define PMU_BASE 0xfd8d0000
+#define PMU_PWR_GATE_SFTCON1 0x8150
+
+#define USB2PHY1_GRF_BASE 0xfd5d4000
+#define USB2PHY2_GRF_BASE 0xfd5d8000
+#define USB2PHY3_GRF_BASE 0xfd5dc000
+#define USB2PHY_GRF_CON2 0x0008
+
+#define PMU1_IOC_BASE 0xfd5f0000
+#define PMU2_IOC_BASE 0xfd5f4000
+
+#define BUS_IOC_BASE 0xfd5f8000
+#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
+#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
+#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
+#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
+#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
+
+#define VCCIO3_5_IOC_BASE 0xfd5fa000
+#define IOC_VCCIO3_5_GPIO2A_DS_H 0x44
+#define IOC_VCCIO3_5_GPIO2B_DS_L 0x48
+#define IOC_VCCIO3_5_GPIO2B_DS_H 0x4c
+#define IOC_VCCIO3_5_GPIO3A_DS_L 0x60
+#define IOC_VCCIO3_5_GPIO3A_DS_H 0x64
+#define IOC_VCCIO3_5_GPIO3C_DS_H 0x74
+
+#define EMMC_IOC_BASE 0xfd5fd000
+#define EMMC_IOC_GPIO2A_DS_L 0x40
+#define EMMC_IOC_GPIO2D_DS_L 0x58
+#define EMMC_IOC_GPIO2D_DS_H 0x5c
+
+#define CRU_BASE 0xfd7c0000
+#define CRU_SOFTRST_CON77 0x0b34
+
+#define PMU1CRU_BASE 0xfd7f0000
+#define PMU1CRU_SOFTRST_CON03 0x0a0c
+#define PMU1CRU_SOFTRST_CON04 0x0a10
+
+#define HDMIRX_NODE_FDT_PATH "/hdmirx-controller at fdee0000"
+#define RK3588_PHY_CONFIG 0xfdee00c0
+
+#include <asm/armv8/mmu.h>
+
+static struct mm_region rk3588_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xf0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x900000000,
+ .phys = 0x900000000,
+ .size = 0x150000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3588_mem_map;
+
+/* GPIO0B_IOMUX_SEL_L */
+enum {
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = GENMASK(3, 0),
+ GPIO0B0_UART0_RX_M1 = 4,
+
+ GPIO0B1_SHIFT = 4,
+ GPIO0B1_MASK = GENMASK(7, 4),
+ GPIO0B1_UART0_TX_M1 = 4,
+};
+
+/* GPIO0C_IOMUX_SEL_H */
+enum {
+ GPIO0C4_SHIFT = 0,
+ GPIO0C4_MASK = GENMASK(3, 0),
+ GPIO0C4_UART0_RX_M0 = 4,
+
+ GPIO0C5_SHIFT = 4,
+ GPIO0C5_MASK = GENMASK(7, 4),
+ GPIO0C5_UART0_TX_M0 = 4,
+};
+
+/* GPIO0B_IOMUX_SEL_H */
+enum {
+ GPIO0B5_SHIFT = 4,
+ GPIO0B5_MASK = GENMASK(7, 4),
+ GPIO0B5_REFER = 8,
+ GPIO0B5_UART2_TX_M0 = 10,
+
+ GPIO0B6_SHIFT = 8,
+ GPIO0B6_MASK = GENMASK(11, 8),
+ GPIO0B6_REFER = 8,
+ GPIO0B6_UART2_RX_M0 = 10,
+};
+
+void board_debug_uart_init(void)
+{
+ __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+
+ /* UART 2 */
+ static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
+
+ /* Refer to BUS_IOC */
+ rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
+ GPIO0B6_MASK | GPIO0B5_MASK,
+ GPIO0B6_REFER << GPIO0B6_SHIFT |
+ GPIO0B5_REFER << GPIO0B5_SHIFT);
+
+ /* UART2_M0 Switch iomux */
+ rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
+ GPIO0B6_MASK | GPIO0B5_MASK,
+ GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
+ GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+
+ if (reg & 0x1)
+ return;
+
+ asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
+ writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+}
+
+static u32 gpio4d_iomux_sel_l = 0xffffffff;
+static u32 gpio4d_iomux_sel_h;
+static u32 gpio0a_iomux_sel_h;
+
+void spl_board_sd_iomux_save(void)
+{
+ struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
+
+ gpio4d_iomux_sel_l = readl(&bus_ioc->gpio4d_iomux_sel_l);
+ gpio4d_iomux_sel_h = readl(&bus_ioc->gpio4d_iomux_sel_h);
+ gpio0a_iomux_sel_h = readl(&pmu1_ioc->gpio0a_iomux_sel_h);
+}
+
+void spl_board_storages_fixup(struct spl_image_loader *loader)
+{
+ int ret = 0;
+
+ if (!loader)
+ return;
+
+ if (loader->boot_device == BOOT_DEVICE_MMC2 && gpio4d_iomux_sel_l != 0xffffffff) {
+ struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ struct rk3588_pmu1_ioc * const pmu1_ioc = (void *)PMU1_IOC_BASE;
+ struct mmc *mmc = NULL;
+ bool no_card;
+
+ ret = spl_mmc_find_device(&mmc, BOOT_DEVICE_MMC2);
+ if (ret)
+ return;
+
+ no_card = mmc_getcd(mmc) == 0;
+ if (no_card) {
+ writel(0xffffuL << 16 | gpio4d_iomux_sel_l, &bus_ioc->gpio4d_iomux_sel_l);
+ writel(0xffffuL << 16 | gpio4d_iomux_sel_h, &bus_ioc->gpio4d_iomux_sel_h);
+ writel(0xffffuL << 16 | gpio0a_iomux_sel_h, &pmu1_ioc->gpio0a_iomux_sel_h);
+ }
+ }
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ int secure_reg;
+
+ /* Set the SDMMC eMMC crypto_ns FSPI access secure area */
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
+ secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
+ secure_reg &= 0xffff0000;
+ writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
+
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
+ secure_reg &= 0xffff;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
+ secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+ secure_reg &= 0xffff0000;
+ writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+
+ /* Select clk_tx source as default for i2s2/i2s3 */
+ writel(0x03400340, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
+
+ if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
+ /* Set the fspi m0 io ds level to 55ohm */
+ writel(0x00070002, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
+ writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
+ writel(0x07000200, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
+ } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x1111) {
+ /*
+ * Set the emmc io drive strength:
+ * data and cmd: 50ohm
+ * clock: 25ohm
+ */
+ writel(0x00770052, EMMC_IOC_BASE + EMMC_IOC_GPIO2A_DS_L);
+ writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_L);
+ writel(0x77772222, EMMC_IOC_BASE + EMMC_IOC_GPIO2D_DS_H);
+ } else if ((readl(BUS_IOC_BASE + BUS_IOC_GPIO2B_IOMUX_SEL_L) & 0xf0ff) == 0x3033) {
+ /* Set the fspi m1 io ds level to 55ohm */
+ writel(0x33002200, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2A_DS_H);
+ writel(0x30332022, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_L);
+ writel(0x00030002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO2B_DS_H);
+ } else if (readl(BUS_IOC_BASE + BUS_IOC_GPIO3A_IOMUX_SEL_L) == 0x5555) {
+ /* Set the fspi m2 io ds level to 55ohm */
+ writel(0x77772222, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_L);
+ writel(0x00700020, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3A_DS_H);
+ writel(0x00070002, VCCIO3_5_IOC_BASE + IOC_VCCIO3_5_GPIO3C_DS_H);
+ }
+
+ /* Set emmc iomux for good extension if the emmc is not the boot device */
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2A_IOMUX_SEL_L);
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
+ writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
+
+ /*
+ * Assert reset the pipephy0, pipephy1 and pipephy2,
+ * and de-assert reset them in Kernel combphy driver.
+ */
+ writel(0x01c001c0, CRU_BASE + CRU_SOFTRST_CON77);
+
+ /*
+ * Assert SIDDQ for USB 2.0 PHY1, PHY2 and PHY3 to
+ * power down all analog block to save power. And
+ * PHY0 for OTG0 interface still in normal mode.
+ */
+ writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON2);
+ writel(0x20002000, USB2PHY2_GRF_BASE + USB2PHY_GRF_CON2);
+ writel(0x20002000, USB2PHY3_GRF_BASE + USB2PHY_GRF_CON2);
+
+ /* Assert hdptxphy init,cmn,lane reset */
+ writel(0xb800b800, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON03);
+ writel(0x00030003, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON04);
+
+ spl_board_sd_iomux_save();
+#endif
+ /* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
+ writel(0x00080008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);
+
+ return 0;
+}
+
+int rk_board_fdt_fixup(const void *blob)
+{
+ int node;
+
+ /* set hdmirx to low power mode */
+ node = fdt_path_offset(blob, HDMIRX_NODE_FDT_PATH);
+ if (node >= 0) {
+ if (fdtdec_get_int(blob, node, "low-power-mode", 0)) {
+ printf("hdmirx low power mode\n");
+ writel(0x00000100, RK3588_PHY_CONFIG);
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
new file mode 100644
index 0000000000..15e4faeb32
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3588_syscon_ids[] = {
+ { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF },
+ { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF },
+ { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF },
+ { .compatible = "rockchip,rk3588-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY0_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY1_GRF },
+ { .compatible = "rockchip,pipe-phy-grf", .data = ROCKCHIP_SYSCON_PIPE_PHY2_GRF },
+ { .compatible = "rockchip,rk3588-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3588) = {
+ .name = "rk3588_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3588_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
new file mode 100644
index 0000000000..9169e9412a
--- /dev/null
+++ b/include/configs/rk3588_common.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ *
+ */
+
+#ifndef __CONFIG_RK3588_COMMON_H
+#define __CONFIG_RK3588_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0xff000000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xf0000000
+
+#define GICD_BASE 0xfe600000
+#define GICR_BASE 0xfe680000
+#define GICC_BASE 0xfe600000
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00500000\0" \
+ "pxefile_addr_r=0x00600000\0" \
+ "fdt_addr_r=0x0a100000\0" \
+ "kernel_addr_r=0x00400000\0" \
+ "kernel_addr_c=0x05480000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#endif
--
2.39.1
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