[PATCH 11/35] pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7
Marek Vasut
marek.vasut+renesas at mailbox.org
Thu Jan 26 21:01:41 CET 2023
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Note that the Kconfig option name has been updated to match the
Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to
PINCTRL_PFC_R8A77960 .
Also note that a new Kconfig option has been added to enable support
for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 .
Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
arch/arm/mach-rmobile/Kconfig.64 | 2 +-
drivers/pinctrl/renesas/Kconfig | 12 +-
drivers/pinctrl/renesas/Makefile | 2 +-
drivers/pinctrl/renesas/pfc-r8a7796.c | 601 ++++++++++----------------
drivers/pinctrl/renesas/pfc.c | 23 +-
5 files changed, 254 insertions(+), 386 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 13f3f5fde43..248a9a84e5d 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -36,7 +36,7 @@ config R8A7796
bool "Renesas SoC R8A7796"
select GICV2
imply CLK_R8A7796
- imply PINCTRL_PFC_R8A7796
+ imply PINCTRL_PFC_R8A77960
config R8A77965
bool "Renesas SoC R8A77965"
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index f1761a87558..8f994d8d769 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -71,11 +71,17 @@ config PINCTRL_PFC_R8A77951
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
-config PINCTRL_PFC_R8A7796
- bool "Renesas RCar Gen3 R8A7796 pin control driver"
+config PINCTRL_PFC_R8A77960
+ bool "Renesas RCar Gen3 R8A77960 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs.
+
+config PINCTRL_PFC_R8A77961
+ bool "Renesas RCar Gen3 R8A77961 pin control driver"
+ depends on PINCTRL_PFC
+ help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs.
config PINCTRL_PFC_R8A77965
bool "Renesas RCar Gen3 R8A77965 pin control driver"
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index e7607329d0e..721c7bdabbb 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
-obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 06cae74fb51..3cc4a3b366a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -70,6 +70,7 @@
PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
+ PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
@@ -1551,7 +1552,7 @@ static const u16 pinmux_data[] = {
* core will do the right thing and skip trying to mux the pin
* while still applying configuration to it.
*/
-#define FM(x) PINMUX_DATA(x##_MARK, 0),
+#define FM(x) PINMUX_DATA(x##_MARK, 0),
PINMUX_STATIC
#undef FM
};
@@ -1832,7 +1833,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
@@ -2047,7 +2048,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
@@ -2460,6 +2461,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
+/* - MLB+ ------------------------------------------------------------------- */
+static const unsigned int mlb_3pin_pins[] = {
+ RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
+};
+static const unsigned int mlb_3pin_mux[] = {
+ MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
+};
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
+
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@@ -3266,20 +3277,13 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
};
-static const unsigned int qspi0_data2_pins[] = {
- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
- PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
-};
-static const unsigned int qspi0_data2_mux[] = {
- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
-};
-static const unsigned int qspi0_data4_pins[] = {
+static const unsigned int qspi0_data_pins[] = {
/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
/* QSPI0_IO2, QSPI0_IO3 */
PIN_QSPI0_IO2, PIN_QSPI0_IO3,
};
-static const unsigned int qspi0_data4_mux[] = {
+static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK,
};
@@ -3291,20 +3295,13 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
};
-static const unsigned int qspi1_data2_pins[] = {
- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
- PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
-};
-static const unsigned int qspi1_data2_mux[] = {
- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
-};
-static const unsigned int qspi1_data4_pins[] = {
+static const unsigned int qspi1_data_pins[] = {
/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
/* QSPI1_IO2, QSPI1_IO3 */
PIN_QSPI1_IO2, PIN_QSPI1_IO3,
};
-static const unsigned int qspi1_data4_mux[] = {
+static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK,
};
@@ -3524,19 +3521,12 @@ static const unsigned int scif_clk_b_mux[] = {
};
/* - SDHI0 ------------------------------------------------------------------ */
-static const unsigned int sdhi0_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 2),
-};
-static const unsigned int sdhi0_data1_mux[] = {
- SD0_DAT0_MARK,
-};
-static const unsigned int sdhi0_data4_pins[] = {
+static const unsigned int sdhi0_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
};
-static const unsigned int sdhi0_data4_mux[] = {
+static const unsigned int sdhi0_data_mux[] = {
SD0_DAT0_MARK, SD0_DAT1_MARK,
SD0_DAT2_MARK, SD0_DAT3_MARK,
};
@@ -3562,19 +3552,12 @@ static const unsigned int sdhi0_wp_mux[] = {
SD0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
-static const unsigned int sdhi1_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(3, 8),
-};
-static const unsigned int sdhi1_data1_mux[] = {
- SD1_DAT0_MARK,
-};
-static const unsigned int sdhi1_data4_pins[] = {
+static const unsigned int sdhi1_data_pins[] = {
/* D[0:3] */
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
-static const unsigned int sdhi1_data4_mux[] = {
+static const unsigned int sdhi1_data_mux[] = {
SD1_DAT0_MARK, SD1_DAT1_MARK,
SD1_DAT2_MARK, SD1_DAT3_MARK,
};
@@ -3600,30 +3583,14 @@ static const unsigned int sdhi1_wp_mux[] = {
SD1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
-static const unsigned int sdhi2_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(4, 2),
-};
-static const unsigned int sdhi2_data1_mux[] = {
- SD2_DAT0_MARK,
-};
-static const unsigned int sdhi2_data4_pins[] = {
- /* D[0:3] */
- RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
- RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
-};
-static const unsigned int sdhi2_data4_mux[] = {
- SD2_DAT0_MARK, SD2_DAT1_MARK,
- SD2_DAT2_MARK, SD2_DAT3_MARK,
-};
-static const unsigned int sdhi2_data8_pins[] = {
+static const unsigned int sdhi2_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
};
-static const unsigned int sdhi2_data8_mux[] = {
+static const unsigned int sdhi2_data_mux[] = {
SD2_DAT0_MARK, SD2_DAT1_MARK,
SD2_DAT2_MARK, SD2_DAT3_MARK,
SD2_DAT4_MARK, SD2_DAT5_MARK,
@@ -3672,30 +3639,14 @@ static const unsigned int sdhi2_ds_mux[] = {
SD2_DS_MARK,
};
/* - SDHI3 ------------------------------------------------------------------ */
-static const unsigned int sdhi3_data1_pins[] = {
- /* D0 */
- RCAR_GP_PIN(4, 9),
-};
-static const unsigned int sdhi3_data1_mux[] = {
- SD3_DAT0_MARK,
-};
-static const unsigned int sdhi3_data4_pins[] = {
- /* D[0:3] */
- RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
- RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
-};
-static const unsigned int sdhi3_data4_mux[] = {
- SD3_DAT0_MARK, SD3_DAT1_MARK,
- SD3_DAT2_MARK, SD3_DAT3_MARK,
-};
-static const unsigned int sdhi3_data8_pins[] = {
+static const unsigned int sdhi3_data_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
};
-static const unsigned int sdhi3_data8_mux[] = {
+static const unsigned int sdhi3_data_mux[] = {
SD3_DAT0_MARK, SD3_DAT1_MARK,
SD3_DAT2_MARK, SD3_DAT3_MARK,
SD3_DAT4_MARK, SD3_DAT5_MARK,
@@ -4038,69 +3989,61 @@ static const unsigned int vin4_data18_b_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
};
-static const union vin_data vin4_data_a_pins = {
- .data24 = {
- RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
- RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
- RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
- RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
- RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
- RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
- RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
- RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
- RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
- RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
- RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
- },
+static const unsigned int vin4_data_a_pins[] = {
+ RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
-static const union vin_data vin4_data_a_mux = {
- .data24 = {
- VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
- VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
- VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
- VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
- VI4_DATA8_MARK, VI4_DATA9_MARK,
- VI4_DATA10_MARK, VI4_DATA11_MARK,
- VI4_DATA12_MARK, VI4_DATA13_MARK,
- VI4_DATA14_MARK, VI4_DATA15_MARK,
- VI4_DATA16_MARK, VI4_DATA17_MARK,
- VI4_DATA18_MARK, VI4_DATA19_MARK,
- VI4_DATA20_MARK, VI4_DATA21_MARK,
- VI4_DATA22_MARK, VI4_DATA23_MARK,
- },
+static const unsigned int vin4_data_a_mux[] = {
+ VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+ VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+ VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+ VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
};
-static const union vin_data vin4_data_b_pins = {
- .data24 = {
- RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
- RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
- RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
- RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
- RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
- RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
- RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
- RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
- RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
- RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
- RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
- },
+static const unsigned int vin4_data_b_pins[] = {
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+ RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
};
-static const union vin_data vin4_data_b_mux = {
- .data24 = {
- VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
- VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
- VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
- VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
- VI4_DATA8_MARK, VI4_DATA9_MARK,
- VI4_DATA10_MARK, VI4_DATA11_MARK,
- VI4_DATA12_MARK, VI4_DATA13_MARK,
- VI4_DATA14_MARK, VI4_DATA15_MARK,
- VI4_DATA16_MARK, VI4_DATA17_MARK,
- VI4_DATA18_MARK, VI4_DATA19_MARK,
- VI4_DATA20_MARK, VI4_DATA21_MARK,
- VI4_DATA22_MARK, VI4_DATA23_MARK,
- },
+static const unsigned int vin4_data_b_mux[] = {
+ VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+ VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+ VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+ VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+ VI4_DATA8_MARK, VI4_DATA9_MARK,
+ VI4_DATA10_MARK, VI4_DATA11_MARK,
+ VI4_DATA12_MARK, VI4_DATA13_MARK,
+ VI4_DATA14_MARK, VI4_DATA15_MARK,
+ VI4_DATA16_MARK, VI4_DATA17_MARK,
+ VI4_DATA18_MARK, VI4_DATA19_MARK,
+ VI4_DATA20_MARK, VI4_DATA21_MARK,
+ VI4_DATA22_MARK, VI4_DATA23_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
@@ -4132,29 +4075,25 @@ static const unsigned int vin4_clk_mux[] = {
};
/* - VIN5 ------------------------------------------------------------------- */
-static const union vin_data16 vin5_data_pins = {
- .data16 = {
- RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
- RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
- RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
- RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
- RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
- RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
- },
+static const unsigned int vin5_data_pins[] = {
+ RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+ RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+ RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
-static const union vin_data16 vin5_data_mux = {
- .data16 = {
- VI5_DATA0_MARK, VI5_DATA1_MARK,
- VI5_DATA2_MARK, VI5_DATA3_MARK,
- VI5_DATA4_MARK, VI5_DATA5_MARK,
- VI5_DATA6_MARK, VI5_DATA7_MARK,
- VI5_DATA8_MARK, VI5_DATA9_MARK,
- VI5_DATA10_MARK, VI5_DATA11_MARK,
- VI5_DATA12_MARK, VI5_DATA13_MARK,
- VI5_DATA14_MARK, VI5_DATA15_MARK,
- },
+static const unsigned int vin5_data_mux[] = {
+ VI5_DATA0_MARK, VI5_DATA1_MARK,
+ VI5_DATA2_MARK, VI5_DATA3_MARK,
+ VI5_DATA4_MARK, VI5_DATA5_MARK,
+ VI5_DATA6_MARK, VI5_DATA7_MARK,
+ VI5_DATA8_MARK, VI5_DATA9_MARK,
+ VI5_DATA10_MARK, VI5_DATA11_MARK,
+ VI5_DATA12_MARK, VI5_DATA13_MARK,
+ VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
@@ -4186,9 +4125,9 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[322];
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
- struct sh_pfc_pin_group automotive[30];
+ struct sh_pfc_pin_group common[324];
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
+ struct sh_pfc_pin_group automotive[31];
#endif
} pinmux_groups = {
.common = {
@@ -4212,7 +4151,7 @@ static const struct {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
- SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps),
@@ -4392,11 +4331,11 @@ static const struct {
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(qspi0_ctrl),
- SH_PFC_PIN_GROUP(qspi0_data2),
- SH_PFC_PIN_GROUP(qspi0_data4),
+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl),
- SH_PFC_PIN_GROUP(qspi1_data2),
- SH_PFC_PIN_GROUP(qspi1_data4),
+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4426,28 +4365,28 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
- SH_PFC_PIN_GROUP(sdhi0_data1),
- SH_PFC_PIN_GROUP(sdhi0_data4),
+ BUS_DATA_PIN_GROUP(sdhi0_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi0_data, 4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
- SH_PFC_PIN_GROUP(sdhi1_data1),
- SH_PFC_PIN_GROUP(sdhi1_data4),
+ BUS_DATA_PIN_GROUP(sdhi1_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi1_data, 4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
- SH_PFC_PIN_GROUP(sdhi2_data1),
- SH_PFC_PIN_GROUP(sdhi2_data4),
- SH_PFC_PIN_GROUP(sdhi2_data8),
+ BUS_DATA_PIN_GROUP(sdhi2_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi2_data, 4),
+ BUS_DATA_PIN_GROUP(sdhi2_data, 8),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(sdhi2_ds),
- SH_PFC_PIN_GROUP(sdhi3_data1),
- SH_PFC_PIN_GROUP(sdhi3_data4),
- SH_PFC_PIN_GROUP(sdhi3_data8),
+ BUS_DATA_PIN_GROUP(sdhi3_data, 1),
+ BUS_DATA_PIN_GROUP(sdhi3_data, 4),
+ BUS_DATA_PIN_GROUP(sdhi3_data, 8),
SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(sdhi3_wp),
@@ -4488,34 +4427,36 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
- VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(vin4_data18_a),
- VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
- VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
+ BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(vin4_data18_b),
- VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
- VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
+ BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
+ SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(vin4_clk),
- VIN_DATA_PIN_GROUP(vin5_data, 8),
- VIN_DATA_PIN_GROUP(vin5_data, 10),
- VIN_DATA_PIN_GROUP(vin5_data, 12),
- VIN_DATA_PIN_GROUP(vin5_data, 16),
+ BUS_DATA_PIN_GROUP(vin5_data, 8),
+ BUS_DATA_PIN_GROUP(vin5_data, 10),
+ BUS_DATA_PIN_GROUP(vin5_data, 12),
+ BUS_DATA_PIN_GROUP(vin5_data, 16),
+ SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
@@ -4547,8 +4488,9 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
+ SH_PFC_PIN_GROUP(mlb_3pin),
}
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const char * const audio_clk_groups[] = {
@@ -4607,7 +4549,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
@@ -4649,7 +4591,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
static const char * const du_groups[] = {
"du_rgb666",
@@ -4742,6 +4684,12 @@ static const char * const intc_ex_groups[] = {
"intc_ex_irq5",
};
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
+static const char * const mlb_3pin_groups[] = {
+ "mlb_3pin",
+};
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
+
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
@@ -5056,6 +5004,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
+ "vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@@ -5067,6 +5016,7 @@ static const char * const vin5_groups[] = {
"vin5_data10",
"vin5_data12",
"vin5_data16",
+ "vin5_high8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",
@@ -5075,8 +5025,8 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[52];
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
- struct sh_pfc_function automotive[4];
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
+ struct sh_pfc_function automotive[5];
#endif
} pinmux_functions = {
.common = {
@@ -5133,36 +5083,25 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
-#if defined(CONFIG_PINCTRL_PFC_R8A7796)
+#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
+ SH_PFC_FUNCTION(mlb_3pin),
}
-#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
+#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) FN_##y
#define FM(x) FN_##x
- { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP0_31_16 RESERVED */
GP_0_15_FN, GPSR0_15,
GP_0_14_FN, GPSR0_14,
GP_0_13_FN, GPSR0_13,
@@ -5214,24 +5153,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_1_1_FN, GPSR1_1,
GP_1_0_FN, GPSR1_0, ))
},
- { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+ GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1),
+ GROUP(
+ /* GP2_31_15 RESERVED */
GP_2_14_FN, GPSR2_14,
GP_2_13_FN, GPSR2_13,
GP_2_12_FN, GPSR2_12,
@@ -5248,23 +5174,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_2_1_FN, GPSR2_1,
GP_2_0_FN, GPSR2_0, ))
},
- { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+ GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP3_31_16 RESERVED */
GP_3_15_FN, GPSR3_15,
GP_3_14_FN, GPSR3_14,
GP_3_13_FN, GPSR3_13,
@@ -5282,21 +5196,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_3_1_FN, GPSR3_1,
GP_3_0_FN, GPSR3_0, ))
},
- { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+ GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1),
+ GROUP(
+ /* GP4_31_18 RESERVED */
GP_4_17_FN, GPSR4_17,
GP_4_16_FN, GPSR4_16,
GP_4_15_FN, GPSR4_15,
@@ -5384,35 +5288,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, GPSR6_1,
GP_6_0_FN, GPSR6_0, ))
},
- { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
+ { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+ GROUP(-28, 1, 1, 1, 1),
+ GROUP(
+ /* GP7_31_4 RESERVED */
GP_7_3_FN, GPSR7_3,
GP_7_2_FN, GPSR7_2,
GP_7_1_FN, GPSR7_1,
@@ -5493,12 +5372,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP6_7_4
IP6_3_0 ))
},
- { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
+ GROUP(4, 4, 4, 4, -4, 4, 4, 4),
+ GROUP(
IP7_31_28
IP7_27_24
IP7_23_20
IP7_19_16
- /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* IP7_15_12 RESERVED */
IP7_11_8
IP7_7_4
IP7_3_0 ))
@@ -5603,13 +5484,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP17_7_4
IP17_3_0 ))
},
- { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
- /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
+ GROUP(-24, 4, 4),
+ GROUP(
+ /* IP18_31_8 RESERVED */
IP18_7_4
IP18_3_0 ))
},
@@ -5619,8 +5497,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define F_(x, y) x,
#define FM(x) FN_##x,
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
- GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
- 1, 1, 1, 2, 2, 1, 2, 3),
+ GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
+ 1, 1, 1, 2, 2, 1, 2, -3),
GROUP(
MOD_SEL0_31_30_29
MOD_SEL0_28_27
@@ -5632,7 +5510,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
- 0, 0, /* RESERVED 15 */
+ /* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@@ -5641,12 +5519,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_7_6
MOD_SEL0_5
MOD_SEL0_4_3
- /* RESERVED 2, 1, 0 */
- 0, 0, 0, 0, 0, 0, 0, 0 ))
+ /* RESERVED 2, 1, 0 */ ))
},
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
- 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
+ 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
GROUP(
MOD_SEL1_31_30
MOD_SEL1_29_28_27
@@ -5663,7 +5540,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL1_11
MOD_SEL1_10
MOD_SEL1_9
- 0, 0, 0, 0, /* RESERVED 8, 7 */
+ /* RESERVED 8, 7 */
MOD_SEL1_6
MOD_SEL1_5
MOD_SEL1_4
@@ -5674,7 +5551,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
},
{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
- 1, 4, 4, 4, 3, 1),
+ -16, 1),
GROUP(
MOD_SEL2_31
MOD_SEL2_30
@@ -5688,19 +5565,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL2_19
MOD_SEL2_18
MOD_SEL2_17
- /* RESERVED 16 */
- 0, 0,
- /* RESERVED 15, 14, 13, 12 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 11, 10, 9, 8 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 7, 6, 5, 4 */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- /* RESERVED 3, 2, 1 */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ /* RESERVED 16-1 */
MOD_SEL2_0 ))
},
{ },
@@ -5965,7 +5830,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
{ /* sentinel */ },
};
-static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
@@ -6193,7 +6058,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
[ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
[ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
- [ 7] = SH_PFC_PIN_NONE,
+ [ 7] = PIN_PRESET_N, /* PRESET# */
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
@@ -6222,57 +6087,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ },
};
-static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
- unsigned int pin)
-{
- const struct pinmux_bias_reg *reg;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return PIN_CONFIG_BIAS_DISABLE;
-
- if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
- return PIN_CONFIG_BIAS_DISABLE;
- else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
-}
-
-static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
- unsigned int bias)
-{
- const struct pinmux_bias_reg *reg;
- u32 enable, updown;
- unsigned int bit;
-
- reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
- if (!reg)
- return;
-
- enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
- if (bias != PIN_CONFIG_BIAS_DISABLE)
- enable |= BIT(bit);
-
- updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
- if (bias == PIN_CONFIG_BIAS_PULL_UP)
- updown |= BIT(bit);
-
- sh_pfc_write(pfc, reg->pud, updown);
- sh_pfc_write(pfc, reg->puen, enable);
-}
-
-static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
+static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
- .get_bias = r8a7796_pinmux_get_bias,
- .set_bias = r8a7796_pinmux_set_bias,
+ .get_bias = rcar_pinmux_get_bias,
+ .set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
.name = "r8a774a1_pfc",
- .ops = &r8a7796_pinmux_ops,
+ .ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -6294,10 +6118,37 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
};
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7796
-const struct sh_pfc_soc_info r8a7796_pinmux_info = {
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
+const struct sh_pfc_soc_info r8a77960_pinmux_info = {
.name = "r8a77960_pfc",
- .ops = &r8a7796_pinmux_ops,
+ .ops = &r8a7796_pfc_ops,
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups.common,
+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
+ ARRAY_SIZE(pinmux_groups.automotive),
+ .functions = pinmux_functions.common,
+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
+ ARRAY_SIZE(pinmux_functions.automotive),
+
+ .cfg_regs = pinmux_config_regs,
+ .drive_regs = pinmux_drive_regs,
+ .bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
+
+ .pinmux_data = pinmux_data,
+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
+
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+const struct sh_pfc_soc_info r8a77961_pinmux_info = {
+ .name = "r8a77961_pfc",
+ .ops = &r8a7796_pfc_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 09daaed047a..8f7f9a74b45 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -31,7 +31,8 @@ enum sh_pfc_model {
SH_PFC_R8A7793,
SH_PFC_R8A7794,
SH_PFC_R8A7795,
- SH_PFC_R8A7796,
+ SH_PFC_R8A77960,
+ SH_PFC_R8A77961,
SH_PFC_R8A774A1,
SH_PFC_R8A774B1,
SH_PFC_R8A774C0,
@@ -976,9 +977,13 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A7795)
priv->pfc.info = &r8a77951_pinmux_info;
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7796
- if (model == SH_PFC_R8A7796)
- priv->pfc.info = &r8a7796_pinmux_info;
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
+ if (model == SH_PFC_R8A77960)
+ priv->pfc.info = &r8a77960_pinmux_info;
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+ if (model == SH_PFC_R8A77961)
+ priv->pfc.info = &r8a77961_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
if (model == SH_PFC_R8A774A1)
@@ -1065,10 +1070,16 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.data = SH_PFC_R8A7795,
},
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7796
+#ifdef CONFIG_PINCTRL_PFC_R8A77960
{
.compatible = "renesas,pfc-r8a7796",
- .data = SH_PFC_R8A7796,
+ .data = SH_PFC_R8A77960,
+ },
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77961
+ {
+ .compatible = "renesas,pfc-r8a77961",
+ .data = SH_PFC_R8A77961,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774A1
--
2.39.0
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