[PATCH 07/11] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

Leo Liang ycliang at andestech.com
Tue Jan 31 08:09:10 CET 2023


On Thu, Jan 19, 2023 at 03:05:40PM +0800, Yu Chien Peter Lin wrote:
> This patch refines L1 cache enable/disable and v5l2-cache enable
> functions.
> 
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
>  arch/riscv/cpu/ax25/cache.c | 100 ++++++++++++++++++++++++------------
>  1 file changed, 68 insertions(+), 32 deletions(-)
> 
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>


More information about the U-Boot mailing list