[PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

[Ye Li]

At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li at nxp.com>
Reviewed-by: Peng Fan <peng.fan at nxp.com>
---
 arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index d240aba..104109e 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq)
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
 		;
 
+	clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
+	clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
+
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
-- 
2.7.4