[PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint

[Rick Chen]

Hi Bin,

> From: Bin Meng <bmeng at tinylab.org>
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot at lists.denx.de
> Cc: Anup Patel <anup at brainfault.org>; Atish Patra <atishp at atishpatra.org>; Bin Meng <bmeng.cn at gmail.com>; Palmer Dabbelt <palmer at dabbelt.com>; Paul Walmsley <paul.walmsley at sifive.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>
> Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint
>
> This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform.
>
> The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node.
>
> [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---
>
>  drivers/timer/sifive_clint_timer.c     | 16 +++++++++++-----
>  include/configs/ae350.h                |  2 +-
>  include/configs/qemu-riscv.h           |  2 +-
>  include/configs/sifive-unleashed.h     |  2 +-
>  include/configs/starfive-visionfive2.h |  1 +
>  5 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c
> index 939b99d937..be45f17ddf 100644
> --- a/drivers/timer/sifive_clint_timer.c
> +++ b/drivers/timer/sifive_clint_timer.c
> @@ -12,12 +12,16 @@
>  #include <dm/device-internal.h>
>  #include <linux/err.h>
>
> +#define CLINT_MTIME_OFFSET             0xbff8
> +#define ACLINT_MTIME_OFFSET            0
> +
>  /* mtime register */
> -#define MTIME_REG(base)                        ((ulong)(base) + 0xbff8)
> +#define MTIME_REG(base, offset)                ((ulong)(base) + (offset))
>
>  static u64 notrace sifive_clint_get_count(struct udevice *dev)  {
> -       return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
> +       return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
> +                                              dev_get_driver_data(dev)));
>  }
>
>  #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void)
>   */
>  u64 notrace timer_early_get_count(void)  {
> -       return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
> +       return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
> +                                              RISCV_MMODE_TIMEROFF));
>  }
>  #endif
>
> @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev)  }
>
>  static const struct udevice_id sifive_clint_ids[] = {
> -       { .compatible = "riscv,clint0" },
> -       { .compatible = "sifive,clint0" },
> +       { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
> +       { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
> +       { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
>         { }
>  };
>
> diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296..02c5c80215 100644
> --- a/include/configs/ae350.h
> +++ b/include/configs/ae350.h
> @@ -8,8 +8,8 @@
>  #define __CONFIG_H
>
>  #define RISCV_MMODE_TIMERBASE           0xe6000000
> +#define RISCV_MMODE_TIMEROFF            0xbff8

Why add this for ae350 ?

>  #define RISCV_MMODE_TIMER_FREQ          60000000
> -
>  #define RISCV_SMODE_TIMER_FREQ          60000000
>
>  /*
> diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569e..f6d326bda0 100644
> --- a/include/configs/qemu-riscv.h
> +++ b/include/configs/qemu-riscv.h
> @@ -11,8 +11,8 @@
>  #define CFG_SYS_SDRAM_BASE             0x80000000
>
>  #define RISCV_MMODE_TIMERBASE          0x2000000
> +#define RISCV_MMODE_TIMEROFF           0xbff8
>  #define RISCV_MMODE_TIMER_FREQ         1000000
> -
>  #define RISCV_SMODE_TIMER_FREQ         1000000
>
>  /* Environment options */
> diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
> index de3a0dcdd5..f208f5e20d 100644
> --- a/include/configs/sifive-unleashed.h
> +++ b/include/configs/sifive-unleashed.h
> @@ -14,8 +14,8 @@
>  #define CFG_SYS_SDRAM_BASE             0x80000000
>
>  #define RISCV_MMODE_TIMERBASE          0x2000000
> +#define RISCV_MMODE_TIMEROFF           0xbff8
>  #define RISCV_MMODE_TIMER_FREQ         1000000
> -
>  #define RISCV_SMODE_TIMER_FREQ         1000000
>
>  /* Environment options */
> diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
> index 93dcc22d36..4ee02b8420 100644
> --- a/include/configs/starfive-visionfive2.h
> +++ b/include/configs/starfive-visionfive2.h
> @@ -9,6 +9,7 @@
>  #define _STARFIVE_VISIONFIVE2_H
>
>  #define RISCV_MMODE_TIMERBASE          0x2000000
> +#define RISCV_MMODE_TIMEROFF           0xbff8
>  #define RISCV_MMODE_TIMER_FREQ         4000000
>  #define RISCV_SMODE_TIMER_FREQ         4000000