[PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

[Rick Chen]

> > From: Bin Meng <bmeng at tinylab.org>
> > Sent: Monday, June 12, 2023 3:36 PM
> > To: u-boot at lists.denx.de
> > Cc: Leo Yu-Chi Liang(梁育齊) <ycliang at andestech.com>; Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>
> > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint
> >
> > This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform.
> >
> > The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device.
> >
> > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >
> > Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
> LGTM.

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Reviewed-by: Rick Chen <rick at andestech.com>

>
> Thanks,
> Rick