[PATCH v1 04/17] arch: arm: mach-socfpga: include: mach: add new platform agilex5 mach-socfpga enablement

Jit Loon Lim jit.loon.lim at intel.com
Wed Jun 21 05:15:57 CEST 2023


This is for new platform enablement for agilex5.
Add platform related header files to enable new product.

Signed-off-by: Jit Loon Lim <jit.loon.lim at intel.com>
---
 .../include/mach/base_addr_soc64.h            |  43 +++++-
 .../mach-socfpga/include/mach/clock_manager.h |   5 +-
 .../include/mach/clock_manager_agilex5.h      |  12 ++
 arch/arm/mach-socfpga/include/mach/firewall.h |  42 +++++-
 .../mach-socfpga/include/mach/handoff_soc64.h |  25 +++-
 .../mach-socfpga/include/mach/mailbox_s10.h   |  32 +++--
 .../include/mach/reset_manager_soc64.h        |  33 ++++-
 .../mach-socfpga/include/mach/smmu_agilex5.h  |  30 +++++
 arch/arm/mach-socfpga/include/mach/smmu_s10.h |  73 ++++++++++
 .../include/mach/system_manager_soc64.h       | 126 ++++++++++++++++--
 arch/arm/mach-socfpga/include/mach/timer.h    |  30 +++++
 11 files changed, 419 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_agilex5.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_s10.h

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 3f899fcfa3..4a88770638 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,21 +1,60 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
  */
 
 #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
 #define _SOCFPGA_SOC64_BASE_HARDWARE_H_
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOCFPGA_CCU_ADDRESS			0x1c000000
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS		0x18001000
+#define SOCFPGA_SMMU_ADDRESS			0x16000000
+#define SOCFPGA_OCRAM_FIREWALL_ADDRESS		0x108cc400
+#define SOCFPGA_MAILBOX_ADDRESS			0x10a30000
+#define SOCFPGA_UART0_ADDRESS			0x10c02000
+#define SOCFPGA_UART1_ADDRESS			0x10c02100
+#define SOCFPGA_SPTIMER0_ADDRESS		0x10c03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0x10c03100
+#define SOCFPGA_SYSTIMER0_ADDRESS		0x10d00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0x10d00100
+#define SOCFPGA_L4WD0_ADDRESS			0x10d00200
+#define SOCFPGA_L4WD1_ADDRESS			0x10d00300
+#define SOCFPGA_L4WD2_ADDRESS			0x10d00400
+#define SOCFPGA_L4WD3_ADDRESS			0x10d00500
+#define SOCFPGA_L4WD4_ADDRESS			0x10d00600
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0x10d01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0x10d02000
+#define SOCFPGA_CLKMGR_ADDRESS			0x10d10000
+#define SOCFPGA_RSTMGR_ADDRESS			0x10d11000
+#define SOCFPGA_SYSMGR_ADDRESS			0x10d12000
+#define SOCFPGA_OCRAM_ADDRESS			0x00000000
+#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS		0x18000800
+#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS		0x18000A00
+#define SOCFPGA_FW_TBU2NOC_ADDRESS		0x18000C00
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000 /* TODO */
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100 /* TODO */
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200 /* TODO */
+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300 /* TODO */
+#define SOCFPGA_FIREWALL_TCU			0xffd21400 /* TODO */
+#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV	0xffd24800 /* TODO */
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000 /* TODO */
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000 /* TODO */
+#define GICD_BASE				0x1d000000
+#define GICR_BASE				0x1d060000
+#else
 #define SOCFPGA_CCU_ADDRESS			0xf7000000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_FW_MPFE_SCR_ADDRESS		0xf8020000
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
 	IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
 #else
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
 #endif
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS		0xf8024000
 #define SOCFPGA_SMMU_ADDRESS			0xfa000000
 #define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
@@ -39,10 +78,12 @@
 #define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
 #define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
 #define SOCFPGA_FIREWALL_TCU			0xffd21400
+#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV	0xffd24800
 #define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
 #define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
 #define SOCFPGA_OCRAM_ADDRESS			0xffe00000
 #define GICD_BASE				0xfffc1000
 #define GICC_BASE				0xfffc2000
+#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
 
 #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c4..ef92536662 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2013-2023 Altera Corporation <www.altera.com>
  */
 
 #ifndef _CLOCK_MANAGER_H_
@@ -14,6 +14,7 @@ int cm_wait_for_fsm(void);
 void cm_print_clock_quick_summary(void);
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_SOC64)
 int cm_set_qspi_controller_clk_hz(u32 clk_hz);
@@ -28,6 +29,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #include <asm/arch/clock_manager_s10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include <asm/arch/clock_manager_agilex.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#include <asm/arch/clock_manager_agilex5.h>
 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #include <asm/arch/clock_manager_n5x.h>
 #endif
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
new file mode 100644
index 0000000000..cbad0fdec7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX5_
+#define _CLOCK_MANAGER_AGILEX5_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex5.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX5_ */
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23f8f..8dec4af0f3 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2023 Intel Corporation <www.intel.com>
  *
  */
 
@@ -75,6 +75,8 @@ struct socfpga_firwall_l4_sys {
 };
 
 #define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_ALL	(BIT(0) | BIT(8) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_MPU	BIT(0)
 #define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
 
 /* Cache coherency unit (CCU) registers */
@@ -104,6 +106,13 @@ struct socfpga_firwall_l4_sys {
 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1D		0x2c5a0
 #define CCU_TCU_MPRT_ADBASE_MEMSPACE1E		0x2c5c0
 
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE0		0x105a0
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1A		0x105c0
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1B		0x105e0
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1C		0x10600
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1D		0x10620
+#define CCU_FPGA_MPRT_ADBASE_MEMSPACE1E		0x10640
+
 #define CCU_ADMASK_P_MASK			BIT(0)
 #define CCU_ADMASK_NS_MASK			BIT(1)
 
@@ -126,11 +135,42 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD	0xff
 
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN				0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET			0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE		0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT		0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT		0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT		0x1c
+
+/* Firewall MPFE SCR Registers */
+#define FW_MPFE_SCR_HMC					0x00
+#define FW_MPFE_SCR_HMC_ADAPTOR				0x04
+
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg))
+#else
 #define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
 	writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+#endif
+
+/* Secure Transaction Register */
+#define SECURE_TRANS_OFFS		0x190
+#define SECURE_TRANS_REG		SOCFPGA_SYSMGR_ADDRESS +\
+					SECURE_TRANS_OFFS
+#define SECURE_TRANS_RESET		0x0
+#define SECURE_TRANS_SET		0x33
+#define OCRAM_SECURE_REGION1_OFFS	0x18
+#define OCRAM_SECURE_REGION1_REG	SOCFPGA_OCRAM_FIREWALL_ADDRESS +\
+					OCRAM_SECURE_REGION1_OFFS
+#define NON_SECURE_ACCESS		0x0
 
 void firewall_setup(void);
 
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 902fc6bfb5..27f545734f 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
  *
  */
 
@@ -17,7 +17,12 @@
 #define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
 #define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
 #define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_MAGIC_PERI	0x50455249
+#define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524d
+#else
 #define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
+#endif
 
 #define SOC64_HANDOFF_OFFSET_LENGTH	0x4
 #define SOC64_HANDOFF_OFFSET_DATA	0x10
@@ -27,6 +32,8 @@
 	IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
 #define SOC64_HANDOFF_BASE		0xFFE3F000
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_BASE		0x0007F000
 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #define SOC64_HANDOFF_BASE		0xFFE5F000
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x630)
@@ -58,13 +65,21 @@
 #define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
 #define SOC64_HANDOFF_DELAY		(SOC64_HANDOFF_BASE + 0x3F0)
 #define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_PERI		(SOC64_HANDOFF_BASE + 0x620)
+#define SOC64_HANDOFF_SDRAM		(SOC64_HANDOFF_BASE + 0x634)
+#define SOC64_HANDOFF_SDRAM_LEN		1
+#endif
 
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x608)
-#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x60C)
+#define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x60C)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x614)
 #else
-#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x5fc)
-#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x600)
+#define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x600)
 #endif
 
 #define SOC64_HANDOFF_MUX_LEN			96
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf11597e..502b29bd49 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -112,17 +112,22 @@ enum ALT_SDM_MBOX_RESP_CODE {
 };
 
 /* Mailbox command list */
-#define MBOX_RESTART		2
-#define MBOX_CONFIG_STATUS	4
-#define MBOX_RECONFIG		6
-#define MBOX_RECONFIG_MSEL	7
-#define MBOX_RECONFIG_DATA	8
-#define MBOX_RECONFIG_STATUS	9
+#define MBOX_RESTART			2
+#define MBOX_CONFIG_STATUS		4
+#define MBOX_RECONFIG			6
+#define MBOX_RECONFIG_MSEL		7
+#define MBOX_RECONFIG_DATA		8
+#define MBOX_RECONFIG_STATUS		9
 #define MBOX_VAB_SRC_CERT		11
-#define MBOX_QSPI_OPEN		50
-#define MBOX_QSPI_CLOSE		51
-#define MBOX_QSPI_DIRECT	59
-#define MBOX_REBOOT_HPS		71
+#define MBOX_GET_USERCODE		19
+#define MBOX_QSPI_OPEN			50
+#define MBOX_QSPI_CLOSE			51
+#define MBOX_QSPI_DIRECT		59
+#define MBOX_REBOOT_HPS			71
+#define MBOX_GET_SUBPARTITION_TABLE	90
+#define MBOX_RSU_STATUS			91
+#define MBOX_RSU_UPDATE			92
+#define MBOX_HPS_STAGE_NOTIFY		93
 
 /* Mailbox registers */
 #define MBOX_CIN			0	/* command valid offset */
@@ -166,6 +171,11 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define RCF_SOFTFUNC_STATUS_SEU_ERROR			BIT(3)
 #define RCF_PIN_STATUS_NSTATUS				BIT(31)
 
+/* Defines for HPS_STAGE_NOTIFY */
+#define HPS_EXECUTION_STATE_FSBL	0
+#define HPS_EXECUTION_STATE_SSBL	1
+#define HPS_EXECUTION_STATE_OS		2
+
 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
 		  u32 *resp_buf_len, u32 *resp_buf);
 int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
@@ -182,6 +192,8 @@ int mbox_qspi_open(void);
 #endif
 
 int mbox_reset_cold(void);
+int mbox_hps_stage_notify(u32 execution_stage);
+int mbox_hps_stage_notify_psci(u32 execution_stage);
 int mbox_get_fpga_config_status(u32 cmd);
 int mbox_get_fpga_config_status_psci(u32 cmd);
 #endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727aa2..0f6f1a43da 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,17 +1,25 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *  Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
  */
 
 #ifndef _RESET_MANAGER_SOC64_H_
 #define _RESET_MANAGER_SOC64_H_
 
+#ifndef __ASSEMBLY__
 void reset_deassert_peripherals_handoff(void);
 int cpu_has_been_warmreset(void);
 void print_reset_info(void);
-void socfpga_bridges_reset(int enable);
+void socfpga_bridges_reset(int enable, unsigned int mask);
+void socfpga_bridges_reset_psci(int enable, unsigned int mask);
+void l2_reset_cpu(void);
+void l2_reset_cpu_psci(void);
+#endif
 
 #define RSTMGR_SOC64_STATUS	0x00
+#define RSTMGR_SOC64_HDSKEN	0x10
+#define RSTMGR_SOC64_HDSKREQ	0x14
+#define RSTMGR_SOC64_HDSKACK	0x18
 #define RSTMGR_SOC64_MPUMODRST	0x20
 #define RSTMGR_SOC64_PER0MODRST	0x24
 #define RSTMGR_SOC64_PER1MODRST	0x28
@@ -19,18 +27,33 @@ void socfpga_bridges_reset(int enable);
 
 #define RSTMGR_MPUMODRST_CORE0		0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
+
+#define RSTMGR_BRGMODRST_SOC2FPGA_MASK		BIT(0)
+#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK	BIT(1)
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK		BIT(2)
+#define RSTMGR_BRGMODRST_F2SDRAM0_MASK		BIT(3)
+#define RSTMGR_BRGMODRST_F2SDRAM1_MASK		BIT(4)
+#define RSTMGR_BRGMODRST_F2SDRAM2_MASK		BIT(5)
+#define RSTMGR_BRGMODRST_DDRSCH_MASK		BIT(6)
+
+#define RSTMGR_HDSKEN_FPGAHSEN		BIT(2)
+#define RSTMGR_HDSKREQ_FPGAHSREQ	BIT(2)
 
 /* SDM, Watchdogs and MPU warm reset mask */
-#define RSTMGR_STAT_SDMWARMRST		BIT(1)
+#define RSTMGR_STAT_SDMWARMRST		0x2
 #define RSTMGR_STAT_MPU0RST_BITPOS	8
 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define RSTMGR_STAT_L4WD0RST_BIT	0x1F0000
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	RSTMGR_STAT_SDMWARMRST | \
+		RSTMGR_STAT_L4WD0RST_BIT
+#else
 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
 		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
 			RSTMGR_STAT_MPU0RST_BITPOS) | \
 		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
 			RSTMGR_STAT_L4WD0RST_BITPOS))
+#endif
 
 /*
  * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h b/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h
new file mode 100644
index 0000000000..0bb79896a3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smmu_agilex5.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Intel Corporation. All rights reserved
+ *
+ */
+
+void socfpga_init_smmu(void);
+#define SOCFPGA_NEXT_TBU_PERIPHERAL	4
+/* DMA0 STREAMID */
+#define SYSMGR_DMA0_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x17C
+/* DMA1 STREAMID */
+#define SYSMGR_DMA1_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x180
+/* SDM  STREAMID */
+#define SYSMGR_SDM_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x184
+/* USB2 STREAMID */
+#define SYSMGR_USB2_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x188
+/* USB3 STREAMID, FUTURE USE */
+#define SYSMGR_USB3_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x18C
+/* SDMMC STREAMID */
+#define SYSMGR_SDMMC_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x190
+/* NAND STREAMID */
+#define SYSMGR_NAND_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x194
+/* ETR STREAMID */
+#define SYSMGR_ETR_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x198
+/* TSN0 STREAMID */
+#define SYSMGR_TSN0_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x19C
+/* TSN1 STREAMID */
+#define SYSMGR_TSN1_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x1A0
+/* TSN2 STREAMID */
+#define SYSMGR_TSN2_SID_ADDR	SOCFPGA_SYSMGR_ADDRESS + 0x1A4
diff --git a/arch/arm/mach-socfpga/include/mach/smmu_s10.h b/arch/arm/mach-socfpga/include/mach/smmu_s10.h
new file mode 100644
index 0000000000..9fc3c68ba2
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/smmu_s10.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018-2023 Intel Corporation <www.intel.com>
+ *
+ */
+
+/* SMMU registers */
+#define SMMU_SCR0			0
+#define SMMU_SIDR0			0x20
+#define SMMU_SIDR1			0x24
+
+#define SMMU_SCR0_CLIENTPD		BIT(0)
+#define SMMU_SIDR0_NUMSMRG_MASK		GENMASK(7, 0)
+#define SMMU_SIDR1_NUMCB_MASK		GENMASK(7, 0)
+
+/* Stream mapping registers */
+#define SMMU_GR0_SMR(n)			(0x800 + ((n) << 2))
+#define SMMU_SMR_VALID			BIT(31)
+#define SMMU_SMR_MASK			GENMASK(30, 16)
+#define SMMU_SMR_ID			GENMASK(14, 0)
+
+#define SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
+#define SMMU_S2CR_TYPE			GENMASK(17, 16)
+#define SMMU_S2CR_CBNDX			GENMASK(7, 0)
+
+/* Register groups for Context Bank */
+#define SMMU_GR0_CB(n, r)		(0x20000 + ((n) << 12) + ((r) << 2))
+#define SMMU_CB_SCTLR			0
+#define SMMU_CB_SCTLR_M			BIT(0)
+
+#define SMMU_SID_SDM2HPS_PSI_BE		0
+
+#define SDM2HPS_PSI_BE_ADDR_BASE	0
+/* PSI BE 512MB address window */
+#define SDM2HPS_PSI_BE_WINDOW_SZ	0x20000000
+#define SDM2HPS_PSI_BE_ADDR_END		\
+	(SDM2HPS_PSI_BE_ADDR_BASE + SDM2HPS_PSI_BE_WINDOW_SZ - 1)
+
+void socfpga_init_smmu(void);
+int is_smmu_bypass(void);
+int is_smmu_stream_id_enabled(u32 stream_id);
+
+#define SMMU_SET_STREAMID(x, r, w)	((x << r) | (x << w))
+
+#define SYSMGR_EMAC0_SID_ADDR	0xffd12050	/* EMAC0 (emac0_ace) */
+#define SYSMGR_EMAC1_SID_ADDR	0xffd12054	/* EMAC0 (emac1_ace) */
+#define SYSMGR_EMAC2_SID_ADDR	0xffd12058	/* EMAC0 (emac2_ace) */
+#define SYSMGR_NAND_SID_ADDR	0xffd1205c	/* NAND (nand_axuser) */
+#define SYSMGR_SDMMC_SID_ADDR	0xffd1202c	/* SDMMC (sdmmcgrp_l3master) */
+#define SYSMGR_USB0_SID_ADDR	0xffd12038	/* USB0 (usb0_l3master) */
+#define SYSMGR_USB1_SID_ADDR	0xffd1203c	/* USB0 (usb1_l3master) */
+#define SYSMGR_DMA_SID_ADDR	0xffd12074	/* DMA (dma_l3master) */
+#define SYSMGR_ETR_SID_ADDR	0xffd12078	/* ETR (etr_l3master) */
+
+/* Stream ID field offsets */
+#define EMAC_W_OFST	20
+#define EMAC_R_OFST	8
+#define NAND_W_OFST	0
+#define NAND_R_OFST	16
+#define SDMMC_OFST	16
+#define USB_OFST	16
+#define DMA_W_OFST	0
+#define DMA_R_OFST	16
+#define ETR_W_OFST	0
+#define ETR_R_OFST	16
+
+struct smmu_stream_id {
+	unsigned long addr;
+	u32 sid;
+	u32 r_bit_ofst;
+	u32 w_bit_ofst;
+	u32 secure_bit_offset;
+};
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index a8009664fe..c2b886f8cb 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2023 Intel Corporation <www.intel.com>
  */
 
 #ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -11,11 +11,84 @@ void sysmgr_pinmux_init(void);
 void populate_sysmgr_fpgaintf_module(void);
 void populate_sysmgr_pinmux(void);
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SYSMGR_SOC64_SILICONID_1		0x00
+#define SYSMGR_SOC64_SILICONID_2		0x04
+#define SYSMGR_SOC64_WDDBG			0x08
+#define SYSMGR_SOC64_MPU_STATUS			0x10
+#define SYSMGR_SOC64_SDMMC			0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
+#define SYSMGR_SOC64_COMBOPHY_DFISEL		0xfc
+#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC	0x1
+#define SYSMGR_SOC64_NANDGRP_L3MASTER		0x34
+#define SYSMGR_SOC64_USB0_L3MASTER		0x38
+#define SYSMGR_SOC64_USB1_L3MASTER		0x3c
+#define SYSMGR_SOC64_TSN_GLOBAL			0x40
+#define SYSMGR_SOC64_TSN_0			0x44
+#define SYSMGR_SOC64_TSN_1			0x48
+#define SYSMGR_SOC64_TSN_2			0x4C
+#define SYSMGR_SOC64_TSN_0_ACE			0x50
+#define SYSMGR_SOC64_TSN_1_ACE			0x54
+#define SYSMGR_SOC64_TSN_2_ACE			0x58
+#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2		0x6C
+#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
+#define SYSMGR_SOC64_DMAC0_L3_MASTER		0x74
+#define SYSMGR_SOC64_ETR_L3_MASTER		0x78
+#define SYSMGR_SOC64_DMAC1_L3_MASTER		0x7C
+#define SYSMGR_SOC64_SEC_CTRL_SLT		0x80
+#define SYSMGR_SOC64_OSC_TRIM			0x84
+#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG	0x88
+#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG	0x8C
+#define SYSMGR_SOC64_ECC_INTMASK_VALUE		0x90
+#define SYSMGR_SOC64_ECC_INTMASK_SET		0x94
+#define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
+#define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
+#define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
+#define SYSMGR_SOC64_NOC_TIMEOUT		0xC0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xc4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xc8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xcc
+#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS		0xD4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xD8
+#define SYSMGR_SOC64_FPGA_CONFIG		0xDC
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0	0x200
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1	0x204
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2	0x208
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3	0x20C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4	0x210
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5	0x214
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6	0x218
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7	0x21C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8	0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9	0x224
+#define SYSMGR_SOC64_MPFE_CONFIG	0x228
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258
+
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(31, 0)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT	29
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK	BIT(1)
+#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK	BIT(0)
+
+#define SYSMGR_SOC64_EMAC_GLOBAL	SYSMGR_SOC64_TSN_GLOBAL
+#define SYSMGR_SOC64_EMAC0			SYSMGR_SOC64_TSN_0
+#define SYSMGR_SOC64_EMAC1			SYSMGR_SOC64_TSN_1
+#define SYSMGR_SOC64_EMAC2			SYSMGR_SOC64_TSN_2
+#define SYSMGR_SOC64_EMAC0_ACE		SYSMGR_SOC64_TSN_0_ACE
+#define SYSMGR_SOC64_EMAC1_ACE		SYSMGR_SOC64_TSN_1_ACE
+#define SYSMGR_SOC64_EMAC2_ACE		SYSMGR_SOC64_TSN_2_ACE
+#else
 #define SYSMGR_SOC64_WDDBG			0x08
 #define SYSMGR_SOC64_DMA			0x20
 #define SYSMGR_SOC64_DMA_PERIPH			0x24
 #define SYSMGR_SOC64_SDMMC			0x28
 #define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
+#define SYSMGR_SOC64_NANDGRP_L3MASTER		0x34
+#define SYSMGR_SOC64_USB0_L3MASTER		0x38
+#define SYSMGR_SOC64_USB1_L3MASTER		0x3c
 #define SYSMGR_SOC64_EMAC_GLOBAL		0x40
 #define SYSMGR_SOC64_EMAC0			0x44
 #define SYSMGR_SOC64_EMAC1			0x48
@@ -65,8 +138,37 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
 /* store VBAR_EL3 value */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
+/* store ECC DBE register */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
+/* store ECC DBE address */
 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
+
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
+ * storing qspi ref clock (kHz)
+ */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(27, 0)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK	BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK GENMASK(30, 28)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT	28
+
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8
+ * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ?
+ *
+ * Bit[30] reserved for FSBL to update the DDR init progress
+ * 1 - means in progress, 0 - haven't started / DDR is up running.
+ *
+ * Bit[19] store ATF CPU0 ON OFF value.
+ *
+ * Bit[17:1] - Setting by Linux EDAC.
+ * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1)
+ */
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK	BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK	BIT(30)
+#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
+
 #define SYSMGR_SOC64_PINSEL0			0x1000
 #define SYSMGR_SOC64_IOCTRL0			0x1130
 #define SYSMGR_SOC64_EMAC0_USEFPGA		0x1300
@@ -91,17 +193,23 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_SDMMC_USEFPGA		0x1354
 #define SYSMGR_SOC64_HPS_OSC_CLK		0x1358
 #define SYSMGR_SOC64_IODELAY0			0x1400
+#define SYSMGR_SOC64_PERI			0x15D0
 
 /*
- * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
- * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
- * storing qspi ref clock (kHz)
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8
+ * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ?
+ *
+ * Bit[30] reserved for FSBL to update the DDR init progress
+ * 1 - means in progress, 0 - haven't started / DDR is up running.
+ *
+ * Bit[18] reserved for SDM to configure ACF
+ * Bit[17:1] - Setting by Linux EDAC.
+ * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1)
  */
-#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(27, 0)
-#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK	BIT(31)
-#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK		BIT(30)
-#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK	(BIT(29) | BIT(28))
-#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT	28
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK	BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK	BIT(30)
+#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK	BIT(18)
+#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18
 
 #define SYSMGR_SDMMC				SYSMGR_SOC64_SDMMC
 
diff --git a/arch/arm/mach-socfpga/include/mach/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h
index 82596e412e..ac44b2ea45 100644
--- a/arch/arm/mach-socfpga/include/mach/timer.h
+++ b/arch/arm/mach-socfpga/include/mach/timer.h
@@ -6,6 +6,9 @@
 #ifndef _SOCFPGA_TIMER_H_
 #define _SOCFPGA_TIMER_H_
 
+#include <asm/barriers.h>
+#include <div64.h>
+
 struct socfpga_timer {
 	u32	load_val;
 	u32	curr_val;
@@ -14,4 +17,31 @@ struct socfpga_timer {
 	u32	int_stat;
 };
 
+static __always_inline u64 __socfpga_get_time_stamp(void)
+{
+	u64 cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	return cntpct;
+}
+
+static __always_inline u64 __socfpga_usec_to_tick(u64 usec)
+{
+	u64 tick = usec;
+	u64 cntfrq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+	tick *= cntfrq;
+	do_div(tick, 1000000);
+	return tick;
+}
+
+static __always_inline void __socfpga_udelay(u64 usec)
+{
+	u64 tmp = __socfpga_get_time_stamp() + __socfpga_usec_to_tick(usec);
+
+	while (__socfpga_get_time_stamp() < tmp + 1)
+		;
+}
 #endif
-- 
2.26.2



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