[PATCH v1] arm: socfpga: agilex5: Define MMU mapping region for FPGA

[Jit Loon Lim]

From: Sin Hui Kho <sin.hui.kho at intel.com>

Add MMU mapping region for FPGA including 512 MB LW HPS2FPGA and
1GB HPS2FPGA.

Signed-off-by: Sin Hui Kho <sin.hui.kho at intel.com>
---
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index 0951233cad..c88f0e8632 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -36,6 +36,14 @@ static struct mm_region socfpga_agilex5_mem_map[] = {
 				PTE_BLOCK_NON_SHARE |
 				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
 	}, {
+		/* FPGA 1.5GB */
+		.virt	= 0x20000000UL,
+		.phys	= 0x20000000UL,
+		.size	= 0x60000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	},{
 		/* MEM 2GB */
 		.virt	= 0x80000000UL,
 		.phys	= 0x80000000UL,
-- 
2.26.2