[PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL

[Marc Zyngier]

On Wed, 21 Jun 2023 15:06:51 +0100,
Jit Loon Lim <jit.loon.lim at intel.com> wrote:
> 
> From: Kah Jing Lee <kah.jing.lee at intel.com>
> 
> Dcache feature is not enabled in SPL and enable it will cause ISR
> exception. Since the Dcache is not supported in SPL, new
> CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache
> in SPL.
> 
> Signed-off-by: Kah Jing Lee <kah.jing.lee at intel.com>

This is missing your own SoB.

Now, I'd like to understand what you are actually trying to fix. What
is this 'ISR' exception? This isn't something the architecture
describes. Unless you are using CMOs on something that isn't memory or
for which you don't have a mapping, this should never generate an
exception.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.