[PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL

Marek Vasut marex at denx.de
Wed Jun 21 16:19:14 CEST 2023

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On 6/21/23 16:06, Jit Loon Lim wrote:
> From: Kah Jing Lee <kah.jing.lee at intel.com>
> 
> Dcache feature is not enabled in SPL and enable it will cause ISR
> exception

Why would it cause an exception ?

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