[PATCH V5 9/9] doc: board: ti: am62x_sk: Add A53 SPL DDR layout

[Tom Rini]

On Wed, Jun 21, 2023 at 03:51:18PM +0530, Nikhil M Jain wrote:

> To understand usage of DDR in A53 SPL stage, add a table showing region
> and space used by major components of SPL.
> 
> Signed-off-by: Nikhil M Jain <n-jain1 at ti.com>

Reviewed-by: Tom Rini <trini at konsulko.com>

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20230621/490729ef/attachment.sig>