[PATCH v2 3/3] riscv: Rename SiFive CLINT to RISC-V ALINT

Pali Rohár pali at kernel.org
Sat Jun 24 11:12:24 CEST 2023


I wrote it more times, I'm not risvc maintainer and neither reviewer, so
do not send me these emails because it just spams my inbox and increase
probability that I loose or skip some more important u-boot email.

On Wednesday 21 June 2023 23:11:46 Bin Meng wrote:
> As the RISC-V ACLINT specification is defined to be backward compatible
> with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
> ALINT in the source tree to be future-proof.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Rick Chen <rick at andestech.com>
> 
> ---
> 
> (no changes since v1)
> 
>  MAINTAINERS                                   |  2 +-
>  arch/riscv/Kconfig                            |  8 ++++----
>  arch/riscv/cpu/fu540/Kconfig                  |  2 +-
>  arch/riscv/cpu/fu740/Kconfig                  |  2 +-
>  arch/riscv/cpu/generic/Kconfig                |  4 ++--
>  arch/riscv/cpu/jh7110/Kconfig                 |  2 +-
>  arch/riscv/include/asm/global_data.h          |  4 ++--
>  arch/riscv/include/asm/syscon.h               |  2 +-
>  arch/riscv/lib/Makefile                       |  2 +-
>  .../lib/{sifive_clint.c => aclint_ipi.c}      | 16 +++++++--------
>  board/openpiton/riscv64/Kconfig               |  2 +-
>  board/sipeed/maix/Kconfig                     |  2 +-
>  drivers/timer/Makefile                        |  2 +-
>  ...ive_clint_timer.c => riscv_aclint_timer.c} | 20 +++++++++----------
>  14 files changed, 35 insertions(+), 35 deletions(-)
>  rename arch/riscv/lib/{sifive_clint.c => aclint_ipi.c} (73%)
>  rename drivers/timer/{sifive_clint_timer.c => riscv_aclint_timer.c} (75%)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 228d8af433..91f125aed0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1328,7 +1328,7 @@ F:	doc/arch/riscv.rst
>  F:	doc/usage/sbi.rst
>  F:	drivers/sysreset/sysreset_sbi.c
>  F:	drivers/timer/andes_plmt_timer.c
> -F:	drivers/timer/sifive_clint_timer.c
> +F:	drivers/timer/riscv_aclint_timer.c
>  F:	tools/prelink-riscv.c
>  
>  RISC-V CANAAN KENDRYTE K210
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 9fcdd8c451..de7d5a9549 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -185,22 +185,22 @@ config DMA_ADDR_T_64BIT
>  	bool
>  	default y if 64BIT
>  
> -config SIFIVE_CLINT
> +config RISCV_ACLINT
>  	bool
>  	depends on RISCV_MMODE
>  	select REGMAP
>  	select SYSCON
>  	help
> -	  The SiFive CLINT block holds memory-mapped control and status registers
> +	  The RISC-V ACLINT block holds memory-mapped control and status registers
>  	  associated with software and timer interrupts.
>  
> -config SPL_SIFIVE_CLINT
> +config SPL_RISCV_ACLINT
>  	bool
>  	depends on SPL_RISCV_MMODE
>  	select SPL_REGMAP
>  	select SPL_SYSCON
>  	help
> -	  The SiFive CLINT block holds memory-mapped control and status registers
> +	  The RISC-V ACLINT block holds memory-mapped control and status registers
>  	  associated with software and timer interrupts.
>  
>  config SIFIVE_CACHE
> diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> index 1604b412b4..c68209d8fb 100644
> --- a/arch/riscv/cpu/fu540/Kconfig
> +++ b/arch/riscv/cpu/fu540/Kconfig
> @@ -11,7 +11,7 @@ config SIFIVE_FU540
>  	imply CPU
>  	imply CPU_RISCV
>  	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> -	imply SPL_SIFIVE_CLINT
> +	imply SPL_RISCV_ACLINT
>  	imply CMD_CPU
>  	imply SPL_CPU
>  	imply SPL_OPENSBI
> diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
> index 3e0c1fddc8..d7ca968717 100644
> --- a/arch/riscv/cpu/fu740/Kconfig
> +++ b/arch/riscv/cpu/fu740/Kconfig
> @@ -11,7 +11,7 @@ config SIFIVE_FU740
>  	imply CPU
>  	imply CPU_RISCV
>  	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> -	imply SPL_SIFIVE_CLINT
> +	imply SPL_RISCV_ACLINT
>  	imply CMD_CPU
>  	imply SPL_CPU
>  	imply SPL_OPENSBI
> diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
> index e025134b23..897765c3c6 100644
> --- a/arch/riscv/cpu/generic/Kconfig
> +++ b/arch/riscv/cpu/generic/Kconfig
> @@ -9,8 +9,8 @@ config GENERIC_RISCV
>  	imply CPU
>  	imply CPU_RISCV
>  	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> -	imply SIFIVE_CLINT if RISCV_MMODE
> -	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
> +	imply RISCV_ACLINT if RISCV_MMODE
> +	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
>  	imply CMD_CPU
>  	imply SPL_CPU
>  	imply SPL_OPENSBI
> diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
> index 3f145415eb..4d9581165b 100644
> --- a/arch/riscv/cpu/jh7110/Kconfig
> +++ b/arch/riscv/cpu/jh7110/Kconfig
> @@ -25,4 +25,4 @@ config STARFIVE_JH7110
>  	imply SPL_CPU
>  	imply SPL_LOAD_FIT
>  	imply SPL_OPENSBI
> -	imply SPL_SIFIVE_CLINT
> +	imply SPL_RISCV_ACLINT
> diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
> index 31ba72693d..9d97517e12 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -18,8 +18,8 @@
>  struct arch_global_data {
>  	long boot_hart;		/* boot hart id */
>  	phys_addr_t firmware_fdt_addr;
> -#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
> -	void __iomem *clint;	/* clint base address */
> +#if CONFIG_IS_ENABLED(RISCV_ACLINT)
> +	void __iomem *aclint;	/* aclint base address */
>  #endif
>  #ifdef CONFIG_ANDES_PLICSW
>  	void __iomem *plicsw;	/* andes plicsw base address */
> diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
> index f2b37975f3..5787702e74 100644
> --- a/arch/riscv/include/asm/syscon.h
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -12,7 +12,7 @@
>   */
>  enum {
>  	RISCV_NONE,
> -	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
> +	RISCV_SYSCON_ACLINT,	/* Advanced Core Local Interruptor (ACLINT) */
>  	RISCV_SYSCON_PLICSW,	/* Andes PLICSW */
>  };
>  
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index e5a81ba722..02c4d8fcc6 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -12,7 +12,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y	+= cache.o
>  obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
>  ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += aclint_ipi.o
>  obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
>  else
>  obj-$(CONFIG_SBI) += sbi.o
> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/aclint_ipi.c
> similarity index 73%
> rename from arch/riscv/lib/sifive_clint.c
> rename to arch/riscv/lib/aclint_ipi.c
> index f242168381..90b8e128cb 100644
> --- a/arch/riscv/lib/sifive_clint.c
> +++ b/arch/riscv/lib/aclint_ipi.c
> @@ -29,16 +29,16 @@ int riscv_init_ipi(void)
>  	struct udevice *dev;
>  
>  	ret = uclass_get_device_by_driver(UCLASS_TIMER,
> -					  DM_DRIVER_GET(sifive_clint), &dev);
> +					  DM_DRIVER_GET(riscv_aclint_timer), &dev);
>  	if (ret)
>  		return ret;
>  
>  	if (dev_get_driver_data(dev) != 0)
> -		gd->arch.clint = dev_read_addr_ptr(dev);
> +		gd->arch.aclint = dev_read_addr_ptr(dev);
>  	else
> -		gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT);
> +		gd->arch.aclint = syscon_get_first_range(RISCV_SYSCON_ACLINT);
>  
> -	if (!gd->arch.clint)
> +	if (!gd->arch.aclint)
>  		return -EINVAL;
>  
>  	return 0;
> @@ -46,27 +46,27 @@ int riscv_init_ipi(void)
>  
>  int riscv_send_ipi(int hart)
>  {
> -	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +	writel(1, (void __iomem *)MSIP_REG(gd->arch.aclint, hart));
>  
>  	return 0;
>  }
>  
>  int riscv_clear_ipi(int hart)
>  {
> -	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +	writel(0, (void __iomem *)MSIP_REG(gd->arch.aclint, hart));
>  
>  	return 0;
>  }
>  
>  int riscv_get_ipi(int hart, int *pending)
>  {
> -	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +	*pending = readl((void __iomem *)MSIP_REG(gd->arch.aclint, hart));
>  
>  	return 0;
>  }
>  
>  static const struct udevice_id riscv_aclint_swi_ids[] = {
> -	{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT },
> +	{ .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT },
>  	{ }
>  };
>  
> diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig
> index eb0db8a64c..21da1dc346 100644
> --- a/board/openpiton/riscv64/Kconfig
> +++ b/board/openpiton/riscv64/Kconfig
> @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>  	select SUPPORT_SPL
>  	imply CPU_RISCV
>  	imply RISCV_TIMER
> -	imply SPL_SIFIVE_CLINT
> +	imply SPL_RISCV_ACLINT
>  	imply CMD_CPU
>  	imply SPL_CPU_SUPPORT
>  	imply SPL_SMP
> diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
> index 2d212ec5a3..d34ea4be71 100644
> --- a/board/sipeed/maix/Kconfig
> +++ b/board/sipeed/maix/Kconfig
> @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS
>  	imply SMP
>  	imply DM_SERIAL
>  	imply SIFIVE_SERIAL
> -	imply SIFIVE_CLINT
> +	imply RISCV_ACLINT
>  	imply POWER_DOMAIN
>  	imply SIMPLE_PM_BUS
>  	imply CLK_K210
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index cdc20f5e94..1ca74805fd 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
>  obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
>  obj-$(CONFIG_SANDBOX_TIMER)	+= sandbox_timer.o
>  obj-$(CONFIG_SP804_TIMER)	+= sp804_timer.o
> -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
> +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o
>  obj-$(CONFIG_ARM_GLOBAL_TIMER)	+= arm_global_timer.o
>  obj-$(CONFIG_STM32_TIMER)	+= stm32_timer.o
>  obj-$(CONFIG_TEGRA_TIMER)	+= tegra-timer.o
> diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/riscv_aclint_timer.c
> similarity index 75%
> rename from drivers/timer/sifive_clint_timer.c
> rename to drivers/timer/riscv_aclint_timer.c
> index be45f17ddf..e29d527c8d 100644
> --- a/drivers/timer/sifive_clint_timer.c
> +++ b/drivers/timer/riscv_aclint_timer.c
> @@ -18,7 +18,7 @@
>  /* mtime register */
>  #define MTIME_REG(base, offset)		((ulong)(base) + (offset))
>  
> -static u64 notrace sifive_clint_get_count(struct udevice *dev)
> +static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev)
>  {
>  	return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
>  					       dev_get_driver_data(dev)));
> @@ -44,11 +44,11 @@ u64 notrace timer_early_get_count(void)
>  }
>  #endif
>  
> -static const struct timer_ops sifive_clint_ops = {
> -	.get_count = sifive_clint_get_count,
> +static const struct timer_ops riscv_aclint_timer_ops = {
> +	.get_count = riscv_aclint_timer_get_count,
>  };
>  
> -static int sifive_clint_probe(struct udevice *dev)
> +static int riscv_aclint_timer_probe(struct udevice *dev)
>  {
>  	dev_set_priv(dev, dev_read_addr_ptr(dev));
>  	if (!dev_get_priv(dev))
> @@ -57,18 +57,18 @@ static int sifive_clint_probe(struct udevice *dev)
>  	return timer_timebase_fallback(dev);
>  }
>  
> -static const struct udevice_id sifive_clint_ids[] = {
> +static const struct udevice_id riscv_aclint_timer_ids[] = {
>  	{ .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
>  	{ .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
>  	{ .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
>  	{ }
>  };
>  
> -U_BOOT_DRIVER(sifive_clint) = {
> -	.name		= "sifive_clint",
> +U_BOOT_DRIVER(riscv_aclint_timer) = {
> +	.name		= "riscv_aclint_timer",
>  	.id		= UCLASS_TIMER,
> -	.of_match	= sifive_clint_ids,
> -	.probe		= sifive_clint_probe,
> -	.ops		= &sifive_clint_ops,
> +	.of_match	= riscv_aclint_timer_ids,
> +	.probe		= riscv_aclint_timer_probe,
> +	.ops		= &riscv_aclint_timer_ops,
>  	.flags		= DM_FLAG_PRE_RELOC,
>  };
> -- 
> 2.25.1
> 


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