[PATCH v2] powerpc: Add support for CZ.NIC Turris 1.x routers

Sat Jun 24 11:19:51 CEST 2023

On Monday 12 June 2023 14:07:24 Tom Rini wrote:
> On Wed, Aug 17, 2022 at 10:56:22PM +0200, Pali Rohár wrote:
> 
> > CZ.NIC Turris 1.0 and 1.1 are open source routers, they have dual-core
> > PowerPC Freescale P2020 CPU and are based on Freescale P2020RDB-PC-A board.
> > 
> > Hardware design is fully open source, all firmware and hardware design
> > files are available at Turris project website:
> > 
> > https://docs.turris.cz/hw/turris-1x/turris-1x/
> > https://project.turris.cz/en/hardware.html
> > 
> > This patch adds full U-Boot support for CZ.NIC Turris 1.x routers. P2020
> > BootROM can load U-Boot either from NOR flash or from SD card. So there is
> > defconfig file turris_1x_nor_defconfig which builds NOR version and
> > defconfig file turris_1x_sdcard_defconfig which builds SD card version.
> > 
> > Design of CZ.NIC Turris 1.x routers is based on Freescale P2020RDB-PC-A
> > board, so common board code from boards/freescale/p1_p2_rdb_pc directory is
> > shared and linked also into Turris 1.x U-Boot board code.
> > 
> > Turris 1.x code in this patch uses modern distroboot and can boot Linux
> > kernel from various locations, including NAND, SD card, USB flash disks,
> > NVMe disks or SATA disks (connected to extra SATA/SCSI PCIe controllers).
> > 
> > Signed-off-by: Pali Rohár <pali at kernel.org>
> 
> To be clear, this is something that if there's still interest in
> upstreaming this platform, this patch needs to be rebased and re-tested
> as it's non-trivially out of date.  In addition:

Meanwhile I have already done rebase and retest, v3 is here:
https://patchwork.ozlabs.org/project/uboot/patch/20220831164821.29109-1-pali@kernel.org/

> > diff --git a/board/CZ.NIC/turris_1x/Kconfig b/board/CZ.NIC/turris_1x/Kconfig
> > new file mode 100644
> > index 000000000000..2a1cbd22c783
> > --- /dev/null
> > +++ b/board/CZ.NIC/turris_1x/Kconfig
> > @@ -0,0 +1,170 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +# (C) 2022 Pali Rohár <pali at kernel.org>
> > +
> > +if TARGET_TURRIS_1X
> > +
> > +# Board identification
> > +config SYS_BOARD
> > +	default "turris_1x"
> > +config SYS_VENDOR
> > +	default "CZ.NIC"
> > +config SYS_CONFIG_NAME
> > +	default "turris_1x"
> > +config DEFAULT_DEVICE_TREE
> > +	default "turris1x"
> > +
> > +# Board functions
> > +config ATSHA204A
> > +	default y
> > +config BOARD_EARLY_INIT_F
> > +	default y
> > +config BOARD_EARLY_INIT_R
> > +	default y
> > +config LAST_STAGE_INIT
> > +	default y
> > +config MISC
> > +	default y
> > +config OF_BOARD_FIXUP
> > +	default y
> > +config OF_BOARD_SETUP
> > +	default y
> > +
> > +# ENV
> > +config ENV_SIZE
> > +	default 0x2000
> > +config ENV_SECT_SIZE
> > +	default 0x20000
> > +config ENV_OVERWRITE
> > +	default y
> > +config ENV_IS_IN_FLASH
> > +	default y
> > +config ENV_ADDR
> > +	default 0xeff20000 # in NOR
> > +config SYS_RELOC_GD_ENV_ADDR
> > +	default y
> > +
> > +# DDR
> > +config DDR_CLK_FREQ
> > +	default 66666666
> > +
> > +# UART
> > +config DEBUG_UART_BASE
> > +	default 0xffe04500 if DEBUG_UART
> > +config DEBUG_UART_CLOCK
> > +	default 37500000 if DEBUG_UART
> > +config SYS_NS16550
> > +	default y
> > +
> > +# I2C
> > +config I2C_SET_DEFAULT_BUS_NUM
> > +	default y
> > +config SYS_FSL_I2C_OFFSET
> > +	default 0x3000
> > +config SYS_FSL_HAS_I2C2_OFFSET
> > +	default y
> > +config SYS_FSL_I2C2_OFFSET
> > +	default 0x3100
> > +config SYS_I2C_FSL
> > +	default y
> > +
> > +# GPIO
> > +config MPC8XXX_GPIO
> > +	default y
> > +
> > +# WDT
> > +config WDT_MAX6370
> > +	default y
> > +
> > +# PCIe
> > +config PCI_INIT_R
> > +	default y
> > +config PCIE_FSL
> > +	default y
> > +
> > +# Ethernet
> > +config MII
> > +	default y
> > +config PHY_FIXED
> > +	default y
> > +config TSEC_ENET
> > +	default y
> > +
> > +# USB
> > +config USB_EHCI_FSL
> > +	default y
> > +config USB_XHCI_HCD
> > +	default y
> > +config USB_XHCI_PCI
> > +	default y
> > +
> > +# SDHC
> > +config FSL_ESDHC
> > +	default y
> > +config FSL_PREPBL_ESDHC_BOOT_SECTOR
> > +	default y if SYS_EXTRA_OPTIONS = SDCARD
> > +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH
> > +	default 4
> > +
> > +# NOR
> > +config MTD_NOR_FLASH
> > +	default y
> > +config CFI_FLASH
> > +	default y
> > +config FLASH_CFI_MTD
> > +	default y
> > +config SYS_FLASH_USE_BUFFER_WRITE
> > +	default y
> > +
> > +# NAND
> > +config MTD_RAW_NAND
> > +	default y
> > +config NAND_FSL_ELBC
> > +	default y
> > +config NAND_FSL_ELBC_DT
> > +	default y
> > +config BCH
> > +	default y
> > +config SYS_FLASH_CFI
> > +	default y
> > +
> > +config MPC85XX_HAVE_RESET_VECTOR
> > +	default y if SYS_EXTRA_OPTIONS != SDCARD
> > +
> > +config SYS_LOAD_ADDR
> > +	default 0x1000000
> > +
> > +config SYS_TEXT_BASE
> > +	default 0x11000000 if SPL # in DDR
> > +	default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM
> > +	default 0xeff40000 # in NOR
> > +
> > +if SPL
> > +
> > +config SPL_TEXT_BASE
> > +	default 0xf8f80000 if SYS_EXTRA_OPTIONS = SDCARD # in SRAM
> > +	default 0xeff40000 # in NOR
> > +
> > +config SPL_ENV_SUPPORT
> > +	default y
> > +config SPL_FRAMEWORK
> > +	default n
> > +config SPL_I2C
> > +	default y
> > +config SPL_LIBCOMMON_SUPPORT
> > +	default y
> > +config SPL_LIBGENERIC_SUPPORT
> > +	default y
> > +config SPL_MMC
> > +	default y if SYS_EXTRA_OPTIONS = SDCARD
> > +config SPL_MMC_BOOT
> > +	default y if SYS_EXTRA_OPTIONS = SDCARD
> > +config SPL_MPC8XXX_INIT_DDR
> > +	default y
> > +config SPL_SERIAL
> > +	default y
> > +config SPL_SYS_I2C_LEGACY
> > +	default y
> > +
> > +endif
> > +
> > +endif
> 
> Almost none of this belongs in the board Kconfig file.  Other than
> SYS_BOARD/VENDOR/CONFIG_NAME these all look like normal defconfig
> options.
> 
> And since I suspect you're going to note that this is common to both
> ways of using the platform, I would on the one hand suggest using config
> fragments. But on the other hand, I would really like to see someone
> figure out what we need to do so that they can reside in the board
> directory rather than top-level configs directory, and have the rest of
> the rules work and generate the config appropriately, before we start
> making big use of that feature. Given the rest of your general concerns
> I don't know if you want to spend any time on that or not.

We do not have config fragments support (yet), so I put common
information into Kconfig files.

> [snip]
> > diff --git a/include/configs/turris_1x.h b/include/configs/turris_1x.h
> > new file mode 100644
> > index 000000000000..c53bed028c7a
> > --- /dev/null
> > +++ b/include/configs/turris_1x.h
> > @@ -0,0 +1,390 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +// (C) 2022 Pali Rohár <pali at kernel.org>
> > +
> > +#ifndef _CONFIG_TURRIS_1X_H
> > +#define _CONFIG_TURRIS_1X_H
> > +
> > +#include <linux/sizes.h>
> > +
> > +/*
> > + * Turris 1.x memory map:
> > + *
> > + * 0x0000_0000 - 0x7fff_ffff    2 GB  DDR                 cacheable
> > + * 0x8000_0000 - 0xbfff_ffff    1 GB  PCIe MEM (bus 1-2)  non-cacheable
> > + * 0xc000_0000 - 0xc01f_ffff    2 MB  PCIe MEM (bus 3)    non-cacheable
> > + * 0xc020_0000 - 0xeeff_ffff  750 MB  unused
> > + * 0xef00_0000 - 0xefff_ffff   16 MB  NOR (CS0)           non-cacheable
> > + * 0xf000_0000 - 0xf8f7_ffff  143 MB  unused
> > + * 0xf8f8_0000 - 0xf8ff_ffff  512 kB  L2 SRAM             cacheable (early boot, SD card only)
> > + * 0xf900_0000 - 0xff6f_ffff  103 MB  unused
> > + * 0xff70_0000 - 0xff7f_ffff    1 MB  CCSR                non-cacheable (SPL only)
> > + * 0xff80_0000 - 0xff80_7fff   32 kB  NAND (CS1)          non-cacheable
> > + * 0xffa0_0000 - 0xffa1_ffff  128 kB  CPLD (CS3)          non-cacheable
> > + * 0xffc0_0000 - 0xffc2_ffff  192 kB  PCIe IO             non-cacheable
> > + * 0xffd0_0000 - 0xffd0_3fff   16 kB  L1 stack            cacheable (early boot)
> > + * 0xffe0_0000 - 0xffef_ffff    1 MB  CCSR                non-cacheable (not in SPL)
> > + * 0xffff_f000 - 0xffff_ffff    4 kB  Boot page           non-cacheable
> > + */
> 
> This would belong in a board doc file under doc/board/... and not in
> this header.
> 
> -- 
> Tom

All other mpc85xx boards have this memory mapping in include/configs/*board*.h
header files, so I put it into same place too. So anybody would look for
memory mapping for any mpc85xx board, this information is on the same
place.